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參數(shù)資料
| 型號： | HDMP-0552 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | AGILENT HDMP-0552 QUAD PORT BYPASS CIRCUIT WITH CDR AND DATA VALID DETECTION |
| 中文描述： | 安捷倫劑量甲基強(qiáng)的松龍與CDR和數(shù)據(jù)有效0552四端口旁路電路檢測 |
| 文件頁數(shù)： | 11/12頁 |
| 文件大?。?/td> | 266K |
| 代理商： | HDMP-0552 |
11
Locking Characteristics
Ta = 0
°
C to Tc = +80
°
C , VCC = 3.15 V to 3.45 V
Parameter
Bit Sync Time (phase lock)
Frequency Lock at Powerup
Figure 8 - Setup for Measurement of Random Jitter
Figure 9 - Setup for Measurement of Deterministic Jitter
Units
bits
μs
Maximum
2500
500
70841B
PATTERN
GENERATOR
± DATA
CLOCK
K28.7
0011111000
70311A
CLOCK SOURCE
2.125 GHz
1/20
VARIABLE
DELAY
BIAS
1.4
106.25 MHz
HDMP-0552
± FM_NODE[0]
REF CLK
BYPASS - [0]
BYPASS - [1]
BYPASS - [2]
BYPASS - [3]
BYPASS - [4]
± TO_NODE[1]
83480A
DIGITAL
COMMUNICATION
ANALYZER
TRIGGER
CH 1/2
V
CC
2
2
RANDOM JITTER
70841B
PATTERN
GENERATOR
± DATA
CLOCK
+K28.5 -K28.5
70311A
CLOCK SOURCE
2.125 GHz
1/20
VARIABLE
DELAY
BIAS
1.4
106.25 MHz
HDMP-0552
± FM_NODE[0]
REF CLK
BYPASS - [0]
BYPASS - [1]
BYPASS - [2]
BYPASS - [3]
BYPASS - [4]
± TO_NODE[1]
83480A
DIGITAL
COMMUNICATION
ANALYZER
TRIGGER
CH 1/2
V
CC
2
2
DETERMINISTIC JITTER
1/2
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