參數(shù)資料
型號(hào)： HDMP-0552
廠商： Electronic Theatre Controls, Inc.
英文描述： AGILENT HDMP-0552 QUAD PORT BYPASS CIRCUIT WITH CDR AND DATA VALID DETECTION
中文描述： 安捷倫劑量甲基強(qiáng)的松龍與CDR和數(shù)據(jù)有效0552四端口旁路電路檢測
文件頁數(shù)： 2/12頁
文件大?。?/td> 266K
代理商： HDMP-0552
2
Combinations of Quad PBCs can
be utilized to accommodate any
number of hard disks. The unused
cells in a quad may be bypassed
with pulldown resistors on the
BYPASS[n]- pins for these cells.
Additional power savings possible
by turning off unused output
drives. Please refer to BLL output
section on page 3. An HDMP-0552
can be wired as a single or double
mux cell with a CDR. It may also
be used as a single or double mux
cell without a CDR. All TO_NODE
outputs of the HDMP-0552 are of
equal strength. Therefore, this part
may be used as a 1=>1- 4 buffer.
The design of HDMP-0552 allows
for placement of the CDR at any
location with respect to hard disk
slots. For example, if BYPASS[0]-
pin is tied to V
CC
and hard disk
slots A to D are connected to PBC
cells 1 to 4 in the same order, the
CDR function is performed at
entry to the HDMP-0552 (Figure
2). To achieve a CDR function at
exit from the HDMP-0552,
BYPASS[1]- must be tied to V
CC
and hard disk slots A to D must be
connected to PBC cells 2, 3, 4, 0
in that order (Figure 3). Table 3
shows all possible connections.
In case of CDR at entry, a Signal
Detect (SD) pin shows the status
of the signal at the incoming
cable. The recommended method
of setting the BYPASS[i]- pins
HIGH is to drive them with a
high-impedance signal. Internal
pull-up resistors force the
BYPASS[i]- pins to V
CC
.
HDMP-0552 Block Diagram
CDR
The Clock and Data Recovery
(CDR) block is responsible for
frequency and phase locking onto
the incoming serial data stream
and resampling the incoming data
based on the recovered clock. An
automatic locking feature allows
the CDR to lock onto the input
data stream without external
training controls. It does this by
continually frequency locking
onto the reference clock
(REFCLK) and then phase locking
onto the input data stream. Once
bit-locked, the CDR generates a
high-speed sampling clock. This
clock is used to sample or repeat
the incoming data to produce the
CDR output. The CDR jitter
specifications listed in this data
sheet assume an input that has
been 8B/10B encoded.
Data Valid Output
The outgoing data from the CDR
is checked for two types of errors.
First, the data is checked for “Run
Length Violations” (RLV), which
are defined as a consecutive bit
sequence greater than five. In
addition, the data is checked for
“No Comma Detected” (NCD),
which is defined as no comma
within a 2
15
bit frame. If neither
of these errors occur, the data is
considered valid Fibre Channel
data, and FM_NODE[0]_DV is
driven HIGH.
For reporting errors, the data
valid (DV) block contains a 2
15
-
bit counter to provide a frame
clock. All errors are reported
relative to the rising edge of this
internally generated clock.
There are two LVTTL inputs for
configuring the data validity
checking. When MODE_DV is
HIGH, the data input for the CDR
comes from FM_NODE[0]. In
this mode, the FM_NODE[0]
input is checked for data validity.
In addition, the FM_NODE[0]_DV
LVTTL output can be used to
drive BYPASS[0]- signal. In this
configuration, when the data is
invalid, the CDR output will be
bypassed and the data from
TO_NODE[0] will be passed on
instead.
When MODE_DV is LOW, the
data validity checking is still
taking place on output of the
CDR; however, this data may be
from another input besides
FM_NODE[0]. In addition, the
CDR output data will always be
passed on to TO_NODE[1] in this
mode.
Lastly, the LVTTL input FSEL
selects single versus multi-frame
operation of the DV block. For
example, when FSEL is LOW, the
FM_NODE[0]_DV output will be
driven HIGH after 2
15
bits of good
data. Similarly, FM_NODE[0]_DV
will be driven LOW after one 2
15
bit sequence containing errors.
This is “single frame” operation.
When FSEL is HIGH, the DV block
is operating in “multi-frame”, or
four frame, mode. In this mode,
the FM_NODE[0]_DV will be
driven HIGH only after four
consecutive frames of valid data.
Once HIGH, FM_NODE[0]_DV
will only be driven LOW after
four consecutive 2
15
-bit frames
containing errors.
REFCLK Input and REF_RATE Control
The LVTTL REFCLK input
provides a reference oscillator for
frequency acquisition of the CDR.
The REFCLK frequency should
be 53.125 Mhz or 106.25 Mhz
+100 ppm. Set REF_RATE = 0 for
a 53 Mhz and set REF_RATE = 1
for 106 MHz references. Either
reference frequency can be used
for both 1 GBd or 2 GBd rates.
Amplitude Valid Output
The Amplitude Valid (AV) block
detects if the incoming data on
FM_NODE[0]+ is valid by
examining the differential
amplitude of that input. The
incoming data is considered valid
and FM_NODE[0]_AV is driven
HIGH, as long as the amplitude is
greater than 200 mV (differential
peak-to-peak). FM_NODE[0]_AV
is driven LOW as long as the
amplitude of the input signal is
less than 100 mV (differential
peak-to-peak). When the amplitude
of the input signal is between 100
and 200 mV (differential peak-to-
peak), FM_NODE[0]_AV is
unpredictable.
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