參數(shù)資料
型號(hào)： HC05PL4GRS
英文描述： 68HC05PL4A. 68HC05PL4B. 68HC705PL4B General Release Specification
中文描述： 68HC05PL4A。 68HC05PL4B。 68HC705PL4B一般版本規(guī)范
文件頁數(shù)： 64/98頁
文件大?。?/td> 1004K
代理商： HC05PL4GRS
GENERAL RELEASE SPECIFICATION
April 30, 1998
MOTOROLA
10-2
8-BIT TIMER
MC68HC05PL4
REV 2.0
The counter continues to count after it reaches zero, allowing the software to
determine the number of internal or external clocks since the timer interrupt
request bit (T8IF) was set. The counter may be read at any time by the processor
without disturbing the count. The contents of the counter become stable prior to
the read portion of a cycle and do not change during the read. The timer interrupt
request bit (T8IF) remains set until cleared by writing a “1” to the T8IFR bit in the
T8CR. If writing to the timer 8 counter register (T8CNTR) occurs before the timer
interrupt is served, the interrupt is lost. The T8IF bit may also be used as a
scanned status bit in a non-interrupt mode of operation.
The 3-bit control prescaler is a 7-bit divider which is used to extend the maximum
length of the timer. Bit 0, bit 1 and bit 2 (PS0, PS1 and PS2) of T8CR are pro-
grammed to choose the appropriate prescaler output which is used as the counter
input.
10.2
TIMER8 CONTROL AND STATUS REGISTER (T8CSR)
The T8CSR at address $000D enables the software to control the operation of the
8-bit timer.
T8IF - Timer8 Interrupt Flag
T8IF is set when Timer8 Counter Register counts down to zero. A CPU interrupt
request will be generated if T8IE is set. Writing a "1" to the T8IFR bit clears the
T8IF bit. Writing a "0" to this bit has no effect. Reset clears T8IF.
1 =
Timer8 has count down to zero
0 =
Timer8 has not count down to zero
T8IFR - Timer8 Interrupt Flag Reset
The T8IFR bit is a write-only bit, which clears the T8IF flag by writing “1” to this bit
when the T8IF bit is set. Writing a "0" has no effect. Reset does not affect this bit
1 =
Clear T8IF flag bit
0 =
No effect on T8IF flag bit
T8IE - Interval Timer Interrupt Enable
When this bit is set, a CPU interrupt request is generated when the T8IF bit is set.
Reset clears this bit.
1 =
8-Bit Timer Interrupt enabled
0 =
8-Bit Timer Interrupt disabled
BIT 7
T8IF
BIT 6
0
T8IFR
0
BIT 5
BIT 4
0
BIT 3
BIT 2
BIT 1
BIT 0
T8CSR
$000D
R
W
T8IE
T8EN
PS2
PS1
PS0
reset:
0
Figure 10-2. Timer8 Control and Status Register
0
0
0
1
0
0
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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