- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄371773 > HC05PL4GRS 68HC05PL4A. 68HC05PL4B. 68HC705PL4B General Release Specification PDF資料下載
參數(shù)資料
| 型號： | HC05PL4GRS |
| 英文描述： | 68HC05PL4A. 68HC05PL4B. 68HC705PL4B General Release Specification |
| 中文描述： | 68HC05PL4A。 68HC05PL4B。 68HC705PL4B一般版本規(guī)范 |
| 文件頁數(shù)： | 54/98頁 |
| 文件大小： | 1004K |
| 代理商： | HC05PL4GRS |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁當(dāng)前第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁
GENERAL RELEASE SPECIFICATION
April 30, 1998
MOTOROLA
9-4
16-BIT PROGRAMMABLE TIMER
For More Information On This Product,
Go to: www.freescale.com
MC68HC05PL4
REV 2.0
9.2
ALTERNATE COUNTER REGISTERS (ACRH, ACRL)
The functional block diagram of the 16-bit free-running timer counter and alternate
counter registers is shown in
Figure 9-4
. The alternate counter registers behave
the same as the timer registers, except that any reads of the alternate counter will
not have any effect on the TOF flag bit and Timer interrupts. The alternate counter
registers include a transparent buffer latch on the LSB of the 16-bit timer counter.
Figure 9-4. Alternate Counter Block Diagram
The alternate counter registers (ACRH, ACRL) shown in
Figure 9-5
are read-only
locations which contain the current high and low bytes of the 16-bit free-running
counter. Writing to the alternate counter registers has no effect. Reset of the
device presets the timer counter to $FFFC.
The ACRL latch is a transparent read of the LSB until the a read of the ACRH
takes place. A read of the ACRH latches the LSB into the ACRL location until the
ACRL is again read. The latched value remains fixed even if multiple reads of the
ACRH take place before the next read of the ACRL. Therefore, when reading the
MSB of the timer at ACRH the LSB of the timer at ACRL must also be read to
complete the read sequence.
During power-on-reset (POR), the counter is initialized to $FFFC and begins
counting after the oscillator start-up delay. Because the counter is sixteen bits and
preceded by a fixed divide-by-four prescaler, the value in the counter repeats
every 262,144 internal bus clock cycles (524,288 oscillator cycles).
Reading the ACRH and ACRL in any order or any number of times does not have
any effect on the 16-bit free-running counter or the TOF flag bit.
BIT 7
BIT 6
ACRH6
BIT 5
ACRH5
BIT 4
ACRH4
BIT 3
ACRH3
BIT 2
ACRH2
BIT 1
ACRH1
BIT 0
ACRH0
ACRH
$001A
R ACRH7
W
reset:
1
1
1
1
1
1
1
1
ACRL
$001B
R
W
ACRL7
ACRL6
ACRL5
ACRL4
ACRL3
ACRL2
ACRL1
ACRL0
reset:
1
1
1
1
1
1
0
0
Figure 9-5. Alternate Counter Registers (ACRH, ACRL)
ACRH ($001A)
TMR LSB
16-BIT COUNTER
÷
4
INTERNAL
CLOCK
(XTAL
÷
2)
RESET
ACRL ($001B)
INTERNAL
DATA
BUS
($FFFC)
READ
ACRH
READ
ACRL
READ
LATCH
F
Freescale Semiconductor, Inc.
n
.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HC05V7GRS | 68HC05V7 General Release Specification |
| HC05 | Bipolar Transistor; Transistor Polarity:Dual P Channel; Power Dissipation:20W; DC Current Gain Min (hfe):25; Collector Current:1A; DC Current Gain Max (hfe):200; Power (Ptot):20W |
| HC1-5502A-7 | Subscriber Line Interface Circuit |
| HC4P-5502A-7 | Subscriber Line Interface Circuit |
| HC1062A | Low Voltage Telephone Speech Transmission Circuit / High/Low Level Mute |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HC05V7GRS | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:68HC05V7 General Release Specification |
| HC060WE1DS038B | 制造商:TE Connectivity 功能描述:EC7174-000 |
| HC060YW1DS038B | 制造商:TE Connectivity 功能描述:EC7207-000 |
| HC06B05000J0G | 制造商:FCI 功能描述:OEM ITEM 505-5BNF-SPRING CLAMP SYSTEM |
| HC08 | 制造商:Texas Instruments 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。