- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄371773 > HC05PL4GRS 68HC05PL4A. 68HC05PL4B. 68HC705PL4B General Release Specification PDF資料下載
參數(shù)資料
| 型號： | HC05PL4GRS |
| 英文描述： | 68HC05PL4A. 68HC05PL4B. 68HC705PL4B General Release Specification |
| 中文描述： | 68HC05PL4A。 68HC05PL4B。 68HC705PL4B一般版本規(guī)范 |
| 文件頁數(shù)： | 35/98頁 |
| 文件大?。?/td> | 1004K |
| 代理商： | HC05PL4GRS |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁當(dāng)前第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁
April 30, 1998
GENERAL RELEASE SPECIFICATION
MC68HC05PL4
REV 2.0
RESETS
MOTOROLA
5-3
5.3.1 Power-On Reset (POR)
The internal POR is generated on power-up to allow the clock oscillator to stabi-
lize. The POR is strictly for power turn-on conditions and is not able to detect a
drop in the power supply voltage (brown-out). There is an oscillator stabilization
delay of 4064 internal processor bus clock cycles after the oscillator becomes
active.
The POR will generate the RST signal which will reset the CPU. If any other reset
function is active at the end of the 4096 cycle delay, the RST signal will remain in
the reset condition until the other reset condition(s) end.
POR will not activate the pulldown device on the RESET pin. V
DD
must drop
below V
POR
in order for the internal POR circuit to detect the next rise of V
DD
.
5.3.2 Computer Operating Properly (COP) Reset
The COP watchdog system consist of a divide by 8 counter with clock source from
the 8-bit Timer (Timer8). Hence, a COP watchdog time-out occurs on the 8th
Timer8 clock pulse. A COP watchdog time-out generates a COP reset to the CPU.
Figure 5-3
shows a block diagram of the COP watchdog logic.
Figure 5-3. COP Watchdog Block Diagram
The COP watchdog is part of a software error detection system and must be
cleared periodically to start a new time-out period. To clear the COP watchdog
and prevent a COP reset, write a logic “1” to the COPC bit in the COP register at
location $1FF0. The COP register, shown in
Figure 5-4
, is a write-only register
that returns the content of a ROM location when read.
COPC — COP Clear
COPC is a write-only bit. Periodically writing a logic one to COPC prevents the
COP watchdog from resetting the MCU. Reset clears the COPC bit.
1 =
Reset COP watchdog timer.
0 =
No effect on COP watchdog timer.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
COPR
$1FF0
RESET
R
W
COPC
U
U
U
U
U
U
U
U
Figure 5-4. COP Watchdog Register (COPR)
S
Latch
R
COPON
From Timer8 Counter
÷
8 Counter
COP Reset
To Reset Logic
Write “1” to COPC
R
Logic
From Reset Logic
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HC05V7GRS | 68HC05V7 General Release Specification |
| HC05 | Bipolar Transistor; Transistor Polarity:Dual P Channel; Power Dissipation:20W; DC Current Gain Min (hfe):25; Collector Current:1A; DC Current Gain Max (hfe):200; Power (Ptot):20W |
| HC1-5502A-7 | Subscriber Line Interface Circuit |
| HC4P-5502A-7 | Subscriber Line Interface Circuit |
| HC1062A | Low Voltage Telephone Speech Transmission Circuit / High/Low Level Mute |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HC05V7GRS | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:68HC05V7 General Release Specification |
| HC060WE1DS038B | 制造商:TE Connectivity 功能描述:EC7174-000 |
| HC060YW1DS038B | 制造商:TE Connectivity 功能描述:EC7207-000 |
| HC06B05000J0G | 制造商:FCI 功能描述:OEM ITEM 505-5BNF-SPRING CLAMP SYSTEM |
| HC08 | 制造商:Texas Instruments 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。