參數(shù)資料
型號(hào): HC05K3GRS
英文描述: 68HC05K3 General Release Specification
中文描述: 68HC05K3一般版本規(guī)范
文件頁(yè)數(shù): 68/132頁(yè)
文件大?。?/td> 1188K
代理商: HC05K3GRS
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Technical Data
MC68HC05K3 — Revision 4.0
68
Parallel Input/Output (I/O)
MOTOROLA
Parallel Input/Output (I/O)
If the mask option for software programmable pulldowns is selected, a
floating input can be avoided by first clearing the pulldown register bit
before changing the corresponding DDR from a 1 to a 0. This ensures
that the pulldown device is activated on the pin as the I/O pin changes
from a driven output to a pulled low input.
7.5.5 I/O Pin Truth Tables
Every pin on port A and PB0 on port B may be programmed as an input
or an output under software control, as shown in
Table 7-1
and
Table 7-2
. All port I/O pins also may have software programmable
pulldown devices selected by a mask option. The PB1/OSC3 pin on port
B also can be programmed as an input or an output under software
control,butithasspecialconsiderationswhenselectedbyamaskoption
as an output for the 3-pin RC oscillator, as shown in
Table 7-3
.
Otherwise, PB1/OSC3 behaves the same as PB0.
Table 7-1. Port A Pin Functions
Software
Prog.
Pulldown
Mask
Option*
PDIAx
DDRAx
I/O Pin
Mode
Access to PDRA
at $0010
Access to DDRA
at $0004
Access to Data
Register at $0000
Read
Write
Read/Write
Read
Write
1
X
0
In, Hi-Z
U
PDIA0–PDIA7
DDRA0–DDRA7
I/O pin
X
1
X
1
OUT
U
PDIA0–PDIA7
DDRA0–DDRA7
PA0–PA7
PA0–PA7
0
0
0
In,
Pulldown
U
PDIA0–PDIA7
DDRA0–DDRA7
I/O pin
X
0
0
1
Out
U
PDIA0–PDIA7
DDRA0–DDRA7
PA0–PA7
PA0–PA7
0
1
0
In, Hi-Z
U
PDIA0–PDIA7
DDRA0–DDRA7
I/O pin
X
0
1
1
Out
U
PDIA0–PDIA7
DDRA0–DDRA7
PA0–PA7
PA0–PA7
Notes:
X is don’t care state
U is an undefined state
*1 = pulldowns disabled, 0 = pulldowns enabled
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