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參數(shù)資料
| 型號： | HC05K3GRS |
| 英文描述： | 68HC05K3 General Release Specification |
| 中文描述： | 68HC05K3一般版本規(guī)范 |
| 文件頁數(shù)： | 100/132頁 |
| 文件大?。?/td> | 1188K |
| 代理商： | HC05K3GRS |
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Technical Data
MC68HC05K3 — Revision 4.0
100
Instruction Set
MOTOROLA
Instruction Set
10.3.5 Indexed, No Offset
Indexed instructions with no offset are 1-byte instructions that can
access data with variable addresses within the first 256 memory
locations. The index register contains the low byte of the effective
address of the operand. The CPU automatically uses $00 as the high
byte, so these instructions can address locations $0000–$00FF.
Indexed, no offset instructions are often used to move a pointer through
a table or to hold the address of a frequently used RAM or I/O location.
10.3.6 Indexed, 8-Bit Offset
Indexed, 8-bit offset instructions are 2-byte instructions that can access
data with variable addresses within the first 511 memory locations. The
CPU adds the unsigned byte in the index register to the unsigned byte
following the opcode. The sum is the effective address of the operand.
These instructions can access locations $0000–$01FE.
Indexed 8-bit offset instructions are useful for selecting the kth element
in an n-element table. The table can begin anywhere within the first 256
memory locations and could extend as far as location 510 ($01FE). The
k value is typically in the index register, and the address of the beginning
of the table is in the byte following the opcode.
10.3.7 Indexed,16-Bit Offset
Indexed,16-bitoffsetinstructionsare3-byteinstructionsthatcanaccess
data with variable addresses at any location in memory. The CPU adds
the unsigned byte in the index register to the two unsigned bytes
following the opcode. The sum is the effective address of the operand.
The first byte after the opcode is the high byte of the 16-bit offset; the
second byte is the low byte of the offset.
Indexed,16-bitoffsetinstructionsareusefulforselectingthekthelement
in an n-element table anywhere in memory.
As with direct and extended addressing, the Motorola assembler
determines the shortest form of indexed addressing.
相關PDF資料 |
PDF描述 |
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| HC05PL4GRS | 68HC05PL4A. 68HC05PL4B. 68HC705PL4B General Release Specification |
| HC05V7GRS | 68HC05V7 General Release Specification |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| HC05PL4GRS | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:68HC05PL4A. 68HC05PL4B. 68HC705PL4B General Release Specification |
| HC05V7GRS | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:68HC05V7 General Release Specification |
| HC060WE1DS038B | 制造商:TE Connectivity 功能描述:EC7174-000 |
| HC060YW1DS038B | 制造商:TE Connectivity 功能描述:EC7207-000 |
| HC06B05000J0G | 制造商:FCI 功能描述:OEM ITEM 505-5BNF-SPRING CLAMP SYSTEM |
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