參數(shù)資料
型號: HC05K3GRS
英文描述: 68HC05K3 General Release Specification
中文描述: 68HC05K3一般版本規(guī)范
文件頁數(shù): 60/132頁
文件大小: 1188K
代理商: HC05K3GRS
Technical Data
MC68HC05K3 — Revision 4.0
60
Parallel Input/Output (I/O)
MOTOROLA
Parallel Input/Output (I/O)
7.2 Introduction
Insingle-chipmode,10bidirectionalinput/output(I/O)linesarearranged
asone8-bitI/Oport(portA)andone2-bitI/Oport(portB).Theindividual
bits in these ports are programmable as either inputs or outputs under
software control by the data direction registers (DDRs). All port A and
port B I/O pins have individual software programmable pulldown devices
which can be enabled by a mask option. Some port A pins also have the
additional properties of sinking higher current or acting as additional IRQ
interrupt input sources. One of the port B pins also may be used as an
output for a 3-pin resistor capacitor (RC) oscillator option.
7.3 Port A
PortAisan8-bitbidirectionalportthatsharesfourofitspinswiththeIRQ
interrupt system, as shown in
Figure 7-1
. Each port A pin is controlled
by the corresponding bits in a data direction register, a data register, and
a pulldown register.
Figure 7-1. Port A I/O Circuitry
WRITE $0010
READ $0000
WRITE $0000
READ $0004
DATA
REGISTER BIT
TO IRQ INTERRUPT SYSTEM
(BITS 0-3 ONLY)
I/O
PIN
OUTPUT
MASK OPTION TO INHIBIT
SOFTWARE PULLDOWNS
INTERNAL HC05
DATA BUS
RESET
(RST)
WRITE $0004
DATA DIRECTION
REGISTER BIT
PULLDOWN
REGISTER BIT
V
DD
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