參數(shù)資料
型號: HB52R649E1U-A6B
廠商: ELPIDA MEMORY INC
元件分類: DRAM
英文描述: 64M X 72 SYNCHRONOUS DRAM MODULE, 6.9 ns, DMA168
封裝: DIMM-168
文件頁數(shù): 8/20頁
文件大?。?/td> 151K
代理商: HB52R649E1U-A6B
EOL
Product
HB52R649E1U-A6B/B6B
Preliminary Data Sheet E0022H10
16
AC Characteristics (Ta = 0 to 55°C, V
CC = 3.3 V ± 0.3 V, VSS = 0 V) (cont)
HB52R649E1U
-A6B/B6B
Parameter
Symbol
PC100
Symbol
Min
Max
Unit
Notes
Command setup time
t
CS
Tsi
2.6
ns
1
Command hold time
t
CH
Thi
1.6
ns
1
Ref/Active to Ref/Active command period t
RC
Trc
70
ns
1
Active to precharge command period
t
RAS
Tras
50
120000
ns
1
Active command to column command
(same bank)
t
RCD
Trcd
20
ns
1
Precharge to active command period
t
RP
Trp
20
ns
1
Write recovery or data-in to precharge
lead time
t
DPL
Tdpl
10
ns
1
Active (a) to Active (b) command period
t
RRD
Trrd
20
ns
1
Transition time (rise to fall)
t
T
15ns
Refresh period
t
REF
64
ms
Notes: 1. AC measurement assumes t
T = 1 ns.
Reference level for timing of input signals is 1.5 V.
2. Access time is measured at 1.5 V. Load condition is C
L = 50 pF.
3. t
LZ (max) defines the time at which the outputs achieves the low impedance state.
4. t
HZ (max) defines the time at which the outputs achieves the high impedance state.
5. t
CES defines CKE setup time to CK rising edge except power down exit command.
Test Conditions
Input and output timing reference levels: 1.5 V
Input waveform and output load: See following figures
t
T
2.4 V
0.4 V
0.8 V
2.0 V
input
t
T
DQ
CL
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