參數(shù)資料
型號: HB52R649E1U-A6B
廠商: ELPIDA MEMORY INC
元件分類: DRAM
英文描述: 64M X 72 SYNCHRONOUS DRAM MODULE, 6.9 ns, DMA168
封裝: DIMM-168
文件頁數(shù): 6/20頁
文件大?。?/td> 151K
代理商: HB52R649E1U-A6B
EOL
Product
HB52R649E1U-A6B/B6B
Preliminary Data Sheet E0022H10
14
DC Characteristics (Ta = 0 to 55°C, V
CC = 3.3 V ± 0.3 V, VSS = 0 V)
HB52R649E1U
-A6B
-B6B
Parameter
Symbol
Min
Max
Min
Max
Unit
Test conditions
Notes
Operating current
(
CE latency = 3)
I
CC1
2220
——
mA
Burst length = 1
t
RC = min
1, 2, 3
(
CE latency = 4)
I
CC1
2220
2220
mA
Standby current in power
down
I
CC2P
564
564
mA
CKE = V
IL, tCK = 12
ns
6
Standby current in power
down (input signal stable)
I
CC2PS
546
546
mA
CKE = V
IL, tCK =
7
Standby current in non
power down
I
CC2N
870
870
mA
CKE,
S = V
IH,
t
CK = 12 ns
4
Active standby current in
power down
I
CC3P
582
582
mA
CKE = V
IL, tCK = 12
ns
1, 2, 6
Active standby current in
non power down
I
CC3N
1050
1050
mA
CKE,
S = V
IH,
t
CK = 12 ns
1, 2, 4
Burst operating current
(
CE latency = 3)
I
CC4
2220
——
mA
t
CK = min, BL = 4
1, 2, 5
(
CE latency = 4)
I
CC4
2220
2220
mA
Refresh current
I
CC5
4470
4470
mA
Self refresh current
I
CC6
564
564
mA
V
IH
≥ V
CC – 0.2 V
V
IL
≤ 0.2 V
8
Input leakage current
I
LI
–10
10
–10
10
A
0
≤ Vin ≤ V
CC
Output leakage current
I
LO
–10
10
–10
10
A
0
≤ Vout ≤ V
CC
DQ = disable
Output high voltage
V
OH
2.4
2.4
VI
OH = –4 mA
Output low voltage
V
OL
0.4
0.4
V
I
OL = 4 mA
Notes: 1. I
CC depends on output load condition when the device is selected.
I
CC (max) is specified at the
output open condition.
2. One bank operation.
3. Input signals are changed once per one clock.
4. Input signals are changed once per two clocks.
5. Input signals are changed once per four clocks.
6. After power down mode, CK operating current.
7. After power down mode, no CK operating current.
8. After self refresh mode set, self refresh current.
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