- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄383036 > GS8180D09 (GSI TECHNOLOGY) 2Mb x 9Bit Separate I/O Sigma DDR SRAM(2M x 9位獨(dú)立I/O接口雙數(shù)據(jù)速率讀和寫模式靜態(tài)ΣRAM) PDF資料下載
參數(shù)資料
| 型號(hào)： | GS8180D09 |
| 廠商： | GSI TECHNOLOGY |
| 英文描述： | 2Mb x 9Bit Separate I/O Sigma DDR SRAM(2M x 9位獨(dú)立I/O接口雙數(shù)據(jù)速率讀和寫模式靜態(tài)ΣRAM) |
| 中文描述： | 2MB的x 9Bit分離I / O西格瑪?shù)腄DR SRAM的（2米× 9位獨(dú)立的I / O接口雙數(shù)據(jù)速率讀和寫模式靜態(tài)ΣRAM） |
| 文件頁數(shù)： | 9/33頁 |
| 文件大?。?/td> | 874K |
| 代理商： | GS8180D09 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁當(dāng)前第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁
Rev: 1.01 11/2000
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
9/33
2000, Giga Semiconductor, Inc.
A
Advanced Information
GS8180D09/18B-333/300/275/250
Alternating Read-Write Operations
In order to make interface with Separate I/O Sigma RAMs as straightforward as possible, the control logic has been optimized
specifically for alternate read-write cycles. A Separate I/O Sigma RAM can begin an alternating sequence of reads and writes with
either a read or a write. The status of the W pin is evaluated at the beginning of the first active cycle after the RAM has been
deselected via E1. The status of the W pin is not checked again until the RAM has been deselected and reselected via E1. The user
may introduce as few or as many deselect cycles between active cycles as are desired, but the user must inform the RAM at the
beginning of the first active cycle, via W, whether to restart with a read or write cycle.
All address and control inputs (with the exception of EP2, EP3, and the mode pins, M2–M4) are synchronized to rising clock
edges. Data in is captured on both rising and falling edges of CK. Device activation is accomplished by asserting all three of the
Chip Enable inputs (E1, E2, and E3). Deassertion of any one of the Enable inputs will deactivate the device.
It should be noted
that ONLY deactivation of the RAM via E2 and/or E3 (a Bank Deselect) deactivates the Echo Clocks, CQ1–CQn.
Conversely, only E1 is used to identify a “first active cycle” event.
Read Operations
Read operation will be initiated at the rising edge of clock if the previous cycle was a write and all three chip enables (E1, E2, and
E3) are active. If the previous cycle was a deselect (E1 high), then all three chip enables must be active and the Write enable signal
(W) must be deasserted high. The address presented to the address inputs is latched in to address register and presented to the
memory core and control logic. The control logic determines that a read access is in progress and allows the requested data to
propagate to the input of the output register. At the next rising edge of clock the read data is allowed to propagate through the
output register and onto the Output pins.
Double Data Rate Read
In applications where a data rate markedly faster than the RAM’s latency is desired, Double Data Rate reads double the data
transfer rate (read or write bandwidth) achieved in Pipeline mode while keeping the RAM’s clock frequency constant. In Double
Data Rate mode, the RAM multiplexes the results of a read out of the RAM on half the usual number of data pins. The output
register/mux behaves just as if it were in Pipeline mode for the first transfer, but then makes a second transfer in response to the
next falling edge of clock as well.
Write Operations
Write operation will be initiated at the rising edge of clock if the previous cycle was a read and all three chip enables (E1, E2, and
E3) are active. If the previous cycle was a deselect (E1 high), then all three chip enables must be active and the Write enable signal
(W) must be asserted low. Separate I/O Sigma RAMs employ an “Late Write” protocol, meaning the Address input and the Write
command are due into the RAM on the same rising edge of clock, but Data In is due into the RAM on the next rising edge of clock.
Separate I/O Sigma RAMs accumulate the input data in a register and then feeds the accumulated data into the array at the first
opportunity. Separate I/O Sigma RAMs are fully coherent, which is to say, if the user asks for data just written to the RAM, the
most recent copy of the data will be read directly out of the holding registers rather than from the array (which contains stale data).
Double Data Rate Write
Double Data Rate writes mirror the function of DDR reads and double the data transfer rate achieved in single data rate mode while
keeping the RAM’s clock frequency constant. Data in is captured on both rising and falling edges of CK.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GS8180D18 | 1Mb x 18Bit Separate I/O Sigma DDR SRAM(1M x 18位獨(dú)立I/O接口雙數(shù)據(jù)速率讀和寫模式靜態(tài)ΣRAM) |
| GS8180S36 | 512K x 36Bit Separate I/O Sigma DDR SRAM(512K x 36位獨(dú)立I/O接口雙數(shù)據(jù)速率讀和寫模式靜態(tài)ΣRAM) |
| GS8180S18 | 1Mb x 18Bit Separate I/O Sigma DDR SRAM(1M x 18位獨(dú)立I/O接口雙數(shù)據(jù)速率讀和寫模式靜態(tài)ΣRAM) |
| GS8180S09 | 2Mb x 9Bit Separate I/O Sigma DDR SRAM(2M x 9位獨(dú)立I/O接口雙數(shù)據(jù)速率讀和寫模式靜態(tài)ΣRAM) |
| GS820322T-138 | 64K x 32 2M Synchronous Burst SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS8180Q36D-167X | 制造商:GSI Technology 功能描述:512K X 36 (18 MEG)SIGMA QUAD I -SEPERATE I/O BURST OF 2 - Trays |
| GS8180QV36BGD-167 | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 2.5V 18MBIT 512KX36 2.5NS 165FPBGA - Trays |
| GS8180QV36BGD-167I | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 2.5V 18MBIT 512KX36 2.5NS 165FPBGA - Trays |
| GS8182D08BD-167 | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 1.8V 16MBIT 2MX8 0.5NS 165FPBGA - Trays |
| GS8182D08BD-250 | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 1.8V 16MBIT 2MX8 0.45NS 165FPBGA - Trays |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。