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參數(shù)資料
| 型號： | GS8180D09 |
| 廠商： | GSI TECHNOLOGY |
| 英文描述： | 2Mb x 9Bit Separate I/O Sigma DDR SRAM(2M x 9位獨立I/O接口雙數(shù)據(jù)速率讀和寫模式靜態(tài)ΣRAM) |
| 中文描述： | 2MB的x 9Bit分離I / O西格瑪?shù)腄DR SRAM的（2米× 9位獨立的I / O接口雙數(shù)據(jù)速率讀和寫模式靜態(tài)ΣRAM） |
| 文件頁數(shù)： | 14/33頁 |
| 文件大?。?/td> | 874K |
| 代理商： | GS8180D09 |
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Rev: 1.01 11/2000
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
14/33
2000, Giga Semiconductor, Inc.
A
Advanced Information
GS8180D09/18B-333/300/275/250
Separate I/O DDR Sigma RAM Truth Table
CK
Previous
State
Control
Inputs
Next
State
D
(t
n +1
)
D
(t
n + 1
)
D
(t
n + 2
)
D
(t
n + 2
)
Q
(t
n + 1
)
CQ
(t
n +1
)
Q
(t
n + 1
)
CQ
(t
n + 1
)
Q
(t
n + 2
)
CQ
(t
n + 2
)
Q
(t
n + 2
)
CQ
(t
n + 2
)
E1
E W
↑
Deselect,
Bank Deselect,
Deselect Read,
Deselect Write
1
F
X
Bank
Deselect
X
—
Hi-Z
—
↑
Write
1
F
X
Bank
Deselect
Bank
Deselect
D2
D3
—
Hi-Z
—
↑
Read
1
F
X
X
—
Q2
CQ2
Hi-Z
Q3
CQ3
Hi-Z
—
↑
Deselect,
Bank Deselect,
Deselect Write
Deselect Read
1
T
X
Deselect
X
—
—
CQ0
CQ1
↑
1
T
X
Deselect
X
—
Hi-Z
—
↑
Write
1
T
X
Deselect
D2
D3
—
Hi-Z
CQ0
Q2
CQ2
Hi-Z
CQ1
Q3
CQ3
—
↑
Read
1
T
X
Deselect
X
—
—
↑
Deselect,
Bank Deselect
0
F
0
Deselect
Write
Deselect
Write
Deselect
Write
Deselect
Read
Deselect
Read
Deselect
Read
X
X
Hi-Z
—
↑
Deselect Read
0
F
X
X
X
Hi-Z
—
↑
Read
0
F
X
X
X
Q2
CQ2
Q3
CQ3
—
↑
Deselect,
Bank Deselect
0
F
1
X
—
Hi-Z
Hi-Z
↑
Deselect Write
0
F
X
X
—
Hi-Z
Hi-Z
↑
Write
0
F
X
D2
D3
—
Hi-Z
Hi-Z
↑
Deselect,
Bank Deselect
Deselect Read
0
T
0
Write
D0
D1
D2
D3
Hi-Z
CQ0
Hi-Z
CQ1
—
↑
0
T
X
Write
D0
D1
D2
D3
Hi-Z
—
↑
Read
0
T
X
Write
D0
D1
D2
D3
Q2
CQ2
Q3
CQ3
—
Notes:
1.
2.
3.
4.
5.
X = Don’t Care, H = High, L = Low. E = T (True) if E2 = 1 and E3 = 0; E = F (False) if E2 = 0 or E3 = 1.
D0, D1, D2 and D3 are the first through fourth data input transfers in a write.
Q0, Q1, Q2 and Q3 are the first through fourth data output transfers in a read.
CQ0, CQ1, CQ2 and CQ3 are the echo clocks associated with the first through fourth data transfers.
“—” indicates that the input needed or driver state is determined by a subsequent operation.
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