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參數(shù)資料
| 型號(hào)： | GS8170S36 |
| 廠商： | GSI TECHNOLOGY |
| 英文描述： | 16Mb（512K x 36Bit）Synchronous SRAM(16M位（512K x 36位）同步靜態(tài)RAM) |
| 中文描述： | 16Mb的（為512k × 36Bit）同步SRAM（1,600位（為512k × 36位）同步靜態(tài)內(nèi)存） |
| 文件頁數(shù)： | 32/38頁 |
| 文件大小： | 934K |
| 代理商： | GS8170S36 |
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Rev: 1.01 11/2000
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
32/38
2000, Giga Semiconductor, Inc.
A
Advanced Information
GS8170S18/36/72B-333/300/275/250
in the scan path.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is loaded in the Instruc-
tion Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and I/O buffers into the Boundary Scan
Register. Because the RAM clock is independent from the TAP Clock (TCK) it is possible for the TAP to attempt to capture the I/O ring con-
tents while the input buffers are in transition (i.e., in a metastable state). Although allowing the TAP to sample metastable inputs will not
harm the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the TAP’s input data
capture set-up plus hold time (tTS plus tTH ). The RAM’s clock inputs need not be paused for any other TAP operation except capturing the
I/O ring contents into the Boundary Scan Register. Moving the controller to Shift-DR state then places the Boundary Scan Register between
the TDI and TDO pins. Because the PRELOAD portion of the command is not implemented in this device, moving the controller to the
Update-DR state with the SAMPLE/PRELOAD instruction loaded in the Instruction Register has the same effect as the Pause-DR com-
mand. This functionality is not Standard 1149.1-compliant.
EXTEST (EXTEST-A)
EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register, whatever length it may be in
the device, is loaded with all logic 0s. The EXTEST implementation in this device does not, without further user intervention, actually move
the contents of the scan chain onto the RAM’s output pins. Therefore this device is not strictly 1149.1-compliant. Nevertheless, this RAM’s
TAP does respond to an all 0s instruction, EXTEST (000), by overriding the RAM’s control inputs and activating the Data I/O output drivers.
The RAM’s main clock (CK) may then be used to transfer Boundary Scan Register contents associated with each I/O from the scan register
to the RAM’s output drivers and onto the I/O pins. A single CK transition is sufficient to transfer the data, but more transitions will do no
harm.
IDCODE
The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and places the ID
register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction loaded in at power up and any
time the controller is placed in the Test-Logic-Reset state.
SAMPLE-Z
If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (high-Z) and the
Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR state.
RFU
These instructions are reserved for future use. In this device they replicate the BYPASS instruction.
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| GS8171DW36AGC-300 | 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 1.8V 18MBIT 512KX36 1.8NS 209FBGA - Trays |
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