參數(shù)資料
型號(hào)： GS8170S36
廠商： GSI TECHNOLOGY
英文描述： 16Mb（512K x 36Bit）Synchronous SRAM(16M位（512K x 36位）同步靜態(tài)RAM)
中文描述： 16Mb的（為512k × 36Bit）同步SRAM（1,600位（為512k × 36位）同步靜態(tài)內(nèi)存）
文件頁(yè)數(shù)： 15/38頁(yè)
文件大?。?/td> 934K
代理商： GS8170S36
Rev: 1.01 11/2000
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
15/38
2000, Giga Semiconductor, Inc.
A
Advanced Information
GS8170S18/36/72B-333/300/275/250
Burst Order
The burst address counter wraps around to its initial state after four addresses (the loaded address and three more) have been
accessed. Sigma RAMs always count in linear burst order.
Linear Burst Order
Notes:
1.
The burst counter wraps to initial state on the 5th rising edge of clock.
Output Enable Bus Control
Although the RAM is usually more easily operated in an entirely synchronous mode, a single asynchronous Output Enable pin, G,
is provided. G High overrides all other controls and deselects the output drivers, forcing the drivers into a high impedance state. G
Low returns the RAM to normal synchronous control.
Echo Clock
Σ
RAMs feature Echo Clocks, CQ1,CQ2, CQ1, and CQ2 that track the performance of the output drivers. The Echo Clocks are
delayed copies of the main RAM clock, CK. Echo Clocks are designed to track changes in output driver delays due to variance in
die temperature and supply voltage. The Echo Clocks are designed to fire with the rest of the data output drivers. Sigma RAMs
provide both in-phase, or true, Echo Clock outputs (CQ1 and CQ2) and inverted Echo Clock outputs (CQ1 and CQ2).
A[1:0]
A[1:0]
A[1:0]
A[1:0]
1st address
00
01
10
11
2nd address
01
10
11
00
3rd address
10
11
00
01
4th address
11
00
01
10
Read
C
D
E
Read
Read
/E
1
CK
Address
A
B
Read
Read
ADV
QD
CQ
/G
DQ
QA
QB
QC
Output Enable Control
相關(guān)PDF資料
PDF描述
GS8170S18 16Mb（1M x 18Bit）Synchronous SRAM(16M位（1M x 18位）同步靜態(tài)RAM)
GS8170S72 16Mb（256K x 72Bit）Synchronous SRAM(16M位（256K x 72位）同步靜態(tài)RAM)
GS8180D09 2Mb x 9Bit Separate I/O Sigma DDR SRAM(2M x 9位獨(dú)立I/O接口雙數(shù)據(jù)速率讀和寫(xiě)模式靜態(tài)ΣRAM)
GS8180D18 1Mb x 18Bit Separate I/O Sigma DDR SRAM(1M x 18位獨(dú)立I/O接口雙數(shù)據(jù)速率讀和寫(xiě)模式靜態(tài)ΣRAM)
GS8180S36 512K x 36Bit Separate I/O Sigma DDR SRAM(512K x 36位獨(dú)立I/O接口雙數(shù)據(jù)速率讀和寫(xiě)模式靜態(tài)ΣRAM)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
GS8171DW36AC-300I 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 1.8V 18MBIT 512KX36 1.8NS 209FBGA - Trays
GS8171DW36AC-350 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 1.8V 18MBIT 512KX36 1.7NS 209FBGA - Trays
GS8171DW36AC-350I 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 1.8V 18MBIT 512KX36 1.7NS 209BGA - Trays
GS8171DW36AGC-250 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 1.8V 18MBIT 512KX36 2.1NS 209FBGA - Trays
GS8171DW36AGC-300 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 1.8V 18MBIT 512KX36 1.8NS 209FBGA - Trays
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