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參數(shù)資料
| 型號： | GM5115-H |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | ONPANEL LCD PANEL CONTROLLER |
| 中文描述： | ONPANEL液晶顯示器控制器 |
| 文件頁數(shù)： | 52/58頁 |
| 文件大?。?/td> | 1505K |
| 代理商： | GM5115-H |
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***
Genesis Microchip Confidential ***
gm5115/25 Preliminary Data Sheet
June 2002
43
C5115-DAT-01H
can drive the HFSn line (open drain) depending on whether a read or write operation is being
performed. The gm5115/25 operates as a slave on the interface.
The 2-wire protocol requires each device be addressable by a 7-bit identification number. The
gm5115/25 is initialized on power-up to 2-wire mode by asserting bootstrap pins
HOST_PROTOCOL=0 and the device identification number on HOST_ADDR(6:0) on the rising
edge of RESETn (see Table 18). This provides flexibility in system configuration with multiple
devices that can have the same address.
A 2-wire data transfer consists of a stream of serially transmitted bytes formatted as shown in the
figure below. A transfer is initiated (START) by a high-to-low transition on HFSn while HCLK
is held high. A transfer is terminated by a STOP (a low-to-high transition on HFSn while HCLK
is held high) or by a START (to begin another transfer). The HFSn signal must be stable when
HCLK is high, it may only change when HCLK is low (to avoid being misinterpreted as START
or STOP).
ADDRESS BYTE
HFSn
1
2
3
7
8
9
HCLK
4
5
6
1
2
8
9
DATA BYTE
ACK
ACK
START
STOP
Receiver acknowledges by holding SDA low
R/W
A6
A1
A2
A3
A4
A5
A0
D6
D7
D0
Figure 29.
2-Wire Protocol Data Transfer
Each transaction on the HFSn is in integer multiples of 8 bits (i.e. bytes). The number of bytes
that can be transmitted per transfer is unrestricted. Each byte is transmitted with the most
significant bit (MSB) first. After the eight data bits, the master releases the HFSn line and the
receiver asserts the HFSn line low to acknowledge receipt of the data. The master device
generates the HCLK pulse during the acknowledge cycle. The addressed receiver is obliged to
acknowledge each byte that has been received.
The Write Address Increment and the Write Address No Increment operations allow one or
multiple registers to be programmed with only sending one start address. In Write Address
Increment, the address pointer is automatically incremented after each byte has been sent and
written. The transmission data stream for this mode is illustrated in Figure 30 below. The
highlighted sections of the waveform represent moments when the transmitting device must
release the HFSn line and wait for an acknowledgement from the gm5115/25 (the slave receiver).
ACK
ACK
ACK
OPERATION CODE
START
HFSn
HCLK
STOP
DEVICE ADDRESS
REGISTER ADDRESS
DATA
DATA
R/W
ACK
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
2
9
A8
Two MSBs of register address
A9
Figure 30.
2-Wire Write Operations (0x1x & 0x2x)
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