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參數(shù)資料
| 型號： | GM5115-H |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | ONPANEL LCD PANEL CONTROLLER |
| 中文描述： | ONPANEL液晶顯示器控制器 |
| 文件頁數(shù)： | 51/58頁 |
| 文件大?。?/td> | 1505K |
| 代理商： | GM5115-H |
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***
Genesis Microchip Confidential ***
gm5115/25 Preliminary Data Sheet
June 2002
42
C5115-DAT-01H
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gm5115/25 contains many internal registers that control its operation. These are described in the
gm5115 Family Register Listing (C5115-DSL-01).
A serial host interface is provided to allow an external device to peek and poke registers in the
gm5115/25. This is done using a 2-wire serial protocol. Note that 2-wire host interface requires
bootstrap settings as described in Table 18.
An arbitration mechanism ensures that register accesses from the OCM and the 2-wire host
interface port are always serviced (time division multiplexing).
4.17.1 Host Interface Command Format
Transactions on the 2-wire host protocol occurs in integer multiples of bytes (i.e. 8 bits or two
nibbles respectively). These form an instruction byte, a device register address and/or one or
more data bytes. This is described in Table 19.
The first byte of each transfer indicates the type of operation to be performed by the gm5115/25.
The table below lists the instruction codes and the type of transfer operation. The content of bytes
that follow the instruction byte will vary depending on the instruction chosen. By utilizing these
modes effectively, registers can be quickly configured.
The two LSBs of the instruction code, denoted ‘A9’ and ‘A8’ in Table 19 below, are bits 9 and 8
of the internal register address respectively. Thus, they should be set to ‘00’ to select a starting
register address of less than 256, ‘01’ to select an address in the range 256 to 511, and ‘10’ to
select an address in the range 512 to 767. These bits of the address increment in Address
Increment transfers. The unused bits in the instruction byte, denoted by ‘x’, should be set to ‘1’.
Table 19.
Instruction Byte Map
Operation Mode
Bit
7 6 5 4 3 2 1 0
0 0 0 1 x x A9 A8
0 0 1 0 x x A9 A8
Description
Write Address Increment
Write Address No Increment
(for table loading)
Allows the user to write a single or multiple bytes to a specified starting
address location. A Macro operation will cause the internal address pointer to
increment after each byte transmission. Termination of the transfer will cause
the address pointer to increment to the next address location.
Allows the user to read multiple bytes from a specified starting address
location. A Macro operation will cause the internal address pointer to
increment after each read byte. Termination of the transfer will cause the
address pointer to increment to the next address location.
1 0 0 1 x x A9 A8
1 0 1 0 x x A9 A8
Reserved
Read Address No Increment
(for table reading)
0 0 1 1 x x A9 A8
0 1 0 0 x x A9 A8
1 0 0 0 x x A9 A8
1 0 1 1 x x A9 A8
1 1 0 0 x x A9 A8
0 0 0 0 x x A9 A8
0 1 0 1 x x A9 A8
0 1 1 0 x x A9 A8
0 1 1 1 x x A9 A8
1 1 0 1 x x A9 A8
1 1 1 0 x x A9 A8
1 1 1 1 x x A9 A8
Reserved
Spare
No operation will be performed
4.17.2 2-wire Serial Protocol
The 2-wire protocol consists of a serial clock HCLK (pin number 204) and bi-directional serial
data line HFSn (pin number 205). The bus master drives HCLK and either the master or slave
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