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參數(shù)資料
| 型號： | FS6131-01 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Programmable Line Lock Clock Generator IC |
| 中文描述： | 可編程線鎖定時鐘發(fā)生器IC |
| 文件頁數(shù)： | 9/39頁 |
| 文件大?。?/td> | 435K |
| 代理商： | FS6131-01 |
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9
FS6131-01
Programmable Line Lock Clock Generator IC
5.0
I
2
C-bus Control Interface
This device is a read/write slave device
meeting all Philips I
2
C-bus specifications
except a “general call.” The bus has to be
controlled by a master device that generates
the serial clock SCL, controls bus access, and generates
the START and STOP conditions while the device works
as a slave. Both master and slave can operate as a
transmitter or receiver, but the master device determines
which mode is activated. A device that sends data onto
the bus is defined as the transmitter, and a device re-
ceiving data as the receiver.
I
2
C-bus logic levels noted herein are based on a percent-
age of the power supply (V
DD
). A logic-one corresponds
to a nominal voltage of V
DD
, while a logic-zero corre-
sponds to ground (V
SS
).
5.1
Data transfer on the bus can only be initiated when the
bus is not busy. During the data transfer, the data line
(SDA) must remain stable whenever the clock line (SCL)
is high. Changes in the data line while the clock line is
high will be interpreted by the device as a START or
STOP condition. The following bus conditions are defined
by the I
2
C-bus protocol.
Bus Conditions
5.1.1
Both the data (SDA) and clock (SCL) lines remain high to
indicate the bus is not busy.
Not Busy
5.1.2
A high to low transition of the SDA line while the SCL in-
put is high indicates a START condition. All commands to
the device must be preceded by a START condition.
START Data Transfer
5.1.3
A low to high transition of the SDA line while SCL is held
high indicates a STOP condition. All commands to the
device must be followed by a STOP condition.
STOP Data Transfer
5.1.4
The state of the SDA line represents valid data if the SDA
line is stable for the duration of the high period of the SCL
line after a START condition occurs. The data on the
SDA line must be changed only during the low period of
the SCL signal. There is one clock pulse per data bit.
Data Valid
Each data transfer is initiated by a START condition and
terminated with a STOP condition. The number of data
bytes transferred between START and STOP conditions
is determined by the master device, and can continue
indefinitely. However, data that is overwritten to the de-
vice after the first eight bytes will overflow into the first
register, then the second, and so on, in a first-in, first-
overwritten fashion.
5.1.5
When addressed, the receiving device is required to gen-
erate an Acknowledge after each byte is received. The
master device must generate an extra clock pulse to co-
incide with the Acknowledge bit. The acknowledging de-
vice must pull the SDA line low during the high period of
the master acknowledge clock pulse. Setup and hold
times must be taken into account.
The master must signal an end of data to the slave by not
generating and acknowledge bit on the last byte that has
been read (clocked) out of the slave. In this case, the
slave must leave the SDA line high to enable the master
to generate a STOP condition.
Acknowledge
5.2
All programmable registers can be accessed randomly or
sequentially via this bi-directional two wire digital inter-
face. The crystal oscillator does not have to run for com-
munication to occur.
The device accepts the following I
2
C-bus commands:
I
2
C-bus Operation
5.2.1
After generating a START condition, the bus master
broadcasts a seven-bit slave address followed by a R/W
bit. The address of the device is:
Slave Address
A6
1
A5
0
A4
1
A3
1
A2
X
A1
0
A0
0
where X is controlled by the logic level at the ADDR pin.
The variable ADDR bit allows two different FS6131 de-
vices to exist on the same bus. Note that every device on
an I
2
C-bus must have a unique address to avoid bus
conflicts. The default address sets A2 to 0 via the pull-
down on the ADDR pin.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| FS6131-01G | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:Programmable Line Lock Clock Generator IC |
| FS6131-01G-XTD | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 I2C PROG PLL CLK RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| FS6131-01G-XTP | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 I2C PROG PLL CLK RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| FS6131-01I-XTD | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 I2C PROG PLL CLK (IND) RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| FS6131-01I-XTP | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 I2C PROG PLL CLK IND RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
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