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參數(shù)資料
| 型號： | FS6131-01 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Programmable Line Lock Clock Generator IC |
| 中文描述： | 可編程線鎖定時鐘發(fā)生器IC |
| 文件頁數(shù)： | 8/39頁 |
| 文件大小： | 435K |
| 代理商： | FS6131-01 |
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FS6131-01
Programmable Line Lock Clock Generator IC
4.5.1.2
The direction the loop has gone out-of-range can be de-
termined by clearing STAT[1] to zero and setting STAT[0]
bit to one. If the CMOS bit is set to one, the LOCK/IPRG
pin will go high if the Crystal Loop went out of range high.
If the pin goes to a logic-low, the loop went out of range
low.
The out-of-range information is also available under soft-
ware control by reading back the STAT[1] bit, which is
overwritten by the flag (high = out-of-range high, low =
out-of-range low) in this mode. The bit is set or cleared
only if the Crystal Loop loses lock (see Table 6).
Out-Of-Range High/Low
4.5.1.3
The Crystal Loop is disabled by setting the XLPDEN bit
to a logic-high (1). The bit disables the charge pump cir-
cuit in the loop.
Setting the XLPDEN bit low (0) permits the crystal loop to
operate as a control loop.
Crystal Loop Disable
4.6
Connecting the FS6131 to an
External Reference Frequency
If a crystal oscillator is not used, tie XIN to ground and
shut down the crystal oscillator by setting XLROM[2:0]=1.
The REF and FBK pins do not have pull-up or pull-down
current, but do have a small amount of hysteresis to re-
duce the possibility of extra edges. Signals may be AC-
coupled into these inputs with an external DC-bias circuit
to generate a DC-bias of 2.5V. Any Reference or Feed-
back signal should be square for best results, and the
signals should be rail-to-rail. Unused inputs should be
grounded to avoid unwanted signal injection.
4.7
The differential output stage supports both CMOS and
pseudo-ECL (PECL) signals. The desired output interface
is chosen via the program registers (see Table 4).
If a PECL interface is used, the transmission line is usu-
ally terminated using a Thévenin termination. The output
stage can only sink current in the PECL mode, and the
amount of sink current is set by a programming resistor
on the LOCK/IPRG pin. The ratio of IPRG current to out-
put drive current is shown in Figure 12. Source current is
provided by the pull-up resistor that is part of the
Thévenin termination.
Differential Output Stage
Figure 12: IPRG to CLKP/CLKN Current
0.0
5.0
10.0
15.0
20.0
25.0
0
20
40
60
80
CLKP/CLKN PECL Output Current (mA)
I
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| FS6131-01G | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:Programmable Line Lock Clock Generator IC |
| FS6131-01G-XTD | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 I2C PROG PLL CLK RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| FS6131-01G-XTP | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 I2C PROG PLL CLK RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| FS6131-01I-XTD | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 I2C PROG PLL CLK (IND) RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| FS6131-01I-XTP | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 I2C PROG PLL CLK IND RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
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