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參數資料
| 型號： | FS6131-01 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Programmable Line Lock Clock Generator IC |
| 中文描述： | 可編程線鎖定時鐘發(fā)生器IC |
| 文件頁數： | 37/39頁 |
| 文件大小： | 435K |
| 代理商： | FS6131-01 |
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37
FS6131-01
Programmable Line Lock Clock Generator IC
The output clock frequency is calculated as
15
=
CLK
f
For best performance, program the Post Divider (N
Px
)
modulus to allow the VCO to operate at a nominal fre-
quency that is at least 70MHz but less then 230MHz. The
VCO frequency (f
VCO
) can be calculated by
f
f
=
Selecting the Post Divider modulus of N
Px
=6 is a reason-
able solution, although there are a number of values that
will work. Try to keep
×
Px
F
N
N
to avoid divider values from becoming too large. The set-
tings place the VCO frequency at about 72MHz.
Calculate the ideal charge pump current (I
pump
) as
f
I
15
MHz
0
12
800
kHz
=
×
.
Px
CLK
VCO
N
.
5000
<
VCO
A
lf
lf
Px
F
HSYNC
kHz
pump
C
R
N
N
2
2
×
=
where R
lf
is the external loop filter series resistor, C
lf
is
the external loop filter series capacitor, and A
VCO
is the
VCO gain. The VCO gain is either
A
VCO
=125MHz/V if the High Range is selected, or
A
VCO
=75MHz/V if the Low Range is selected.
See Table 16 for more information on the VCO range.
With f
hsync
=15kHz, C
lf
=0.015
μ
F, R
lf
=15k
, N
F
=800, N
Px
=6,
and A
VCO
=125MHz/V, the charge pump current is 24
μ
A.
A 220pF cap across the entire loop filter is also helpful.
14.2
To generate 800 pixel clocks between HSYNC pulses
occurring on the line reference signal every 15kHz, pro-
gram the following (refer to Figure 32):
Clear the OSCTYPE bit to 0
Turn off the crystal oscillator via XLROM=7
Set the PFD inputs to select the REF and FBK pins
via PDREF=1 and PDFBK=1
Set N
P1
=2, N
P2
=3, and N
P3
=1 for a combined Post
Divider modulus of N
Px
=6 via POST1[1:0],
POST2[1:0], and POST3[1:0].
Select the external loop filter via EXTLF=1
Set XLVTEN=0 and XLPDEN=1 to disable the VCXO
fine tune and the Crystal Loop Phase Frequency
Detector
Set VCOSPD=1 to select the VCO low speed range
Set MLCP[1:0] to 3 to select the 32
μ
A range
The output clock frequency f
CLK
is 12MHz, with an internal
VCO frequency of 72MHz. Note that the Crystal Loop
was unused in this application.
Example Programming
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相關代理商/技術參數 |
參數描述 |
|---|---|
| FS6131-01G | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:Programmable Line Lock Clock Generator IC |
| FS6131-01G-XTD | 功能描述:時鐘發(fā)生器及支持產品 I2C PROG PLL CLK RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| FS6131-01G-XTP | 功能描述:時鐘發(fā)生器及支持產品 I2C PROG PLL CLK RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| FS6131-01I-XTD | 功能描述:時鐘發(fā)生器及支持產品 I2C PROG PLL CLK (IND) RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| FS6131-01I-XTP | 功能描述:時鐘發(fā)生器及支持產品 I2C PROG PLL CLK IND RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
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