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參數(shù)資料
| 型號(hào)： | RTL8801 |
| 英文描述： | Specifications |
| 中文描述： | 規(guī)格 |
| 文件頁(yè)數(shù)： | 10/19頁(yè) |
| 文件大?。?/td> | 318K |
| 代理商： | RTL8801 |
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RTL8801
Preliminary
1999/3
10
Pwr_class
3
rw
Pin
PC0-P
C2
Power class. Controls the value of the pwr field transmitted in
the self-ID packet.
000 - Node does not need power and does not repeat
power
001 - Node is self-powered and provides a minimum of 15
W to the bus
010 - Node is self-powered and provides a minimum of 30
W to the bus.
011 - Node is self-powered and provides a minimum of 45
W to the bus
100 - Node may be powered from the bus and is using up
to 1 W.
101 - Node is powered from the bus and is using up to 1
W. An additional 2 W is needed to enable the link and
higher layers.
110 - Node is powered form the bus and is using up to 1
W. An additional 5 W is needed to enable the link and
higher layers.
111 - Node is powered from the bus and is using up to 1
W. An additional 9 W is needed to enable the link and
higher layers.
The difference between the fastest and slowest repeater data
delay, expressed as (jitter+1)*20ns
Resume interrupt enable. When set to one, the PHY shall set
port_event to one if resume operations commence for any port.
Initiate short (arbitrated) bus reset. A write of one to this bit
instructs the PHY to arbitrate and issue a short bus reset. This bit
is self-clearing.
Loop detect. A write of one to this bit clears it to zero.
Cable power failure detect. Set to one when the PS bit changes
from one to zero. A write of one to this bit clears it to zero.
Arbitration state machine timeout. A write of one to this bit
clears it to zero.
Jitter
3
r
0
Resume_int
1
rw
0
ISBR
1
rw
0
Loop
Pwr_fail
1
1
rw
rw
0
0
Timeout
1
rw
0
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