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參數(shù)資料
| 型號： | EX64-TQG64I |
| 廠商： | Microsemi SoC |
| 文件頁數(shù)： | 9/48頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA ANTIFUSE 3K 64-TQFP |
| 標(biāo)準(zhǔn)包裝： | 160 |
| 系列： | EX |
| 邏輯元件/單元數(shù)： | 128 |
| 輸入/輸出數(shù)： | 41 |
| 門數(shù)： | 3000 |
| 電源電壓： | 2.3 V ~ 2.7 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 64-LQFP |
| 供應(yīng)商設(shè)備封裝： | 64-TQFP（10x10） |
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eX Family FPGAs
Revision 10
1-13
Design Considerations
The TDI, TCK, TDO, PRA, and PRB pins should not be used as input or bidirectional ports. Since these
pins are active during probing, critical signals input through these pins are not available while probing. In
addition, the Security Fuse should not be programmed because doing so disables the probe circuitry. It is
recommended to use a series 70
termination resistor on every probe connector (TDI, TCK, TMS, TDO,
PRA, PRB). The 70
series termination is used to prevent data transmission corruption during probing
and reading back the checksum.
Development Tool Support
The eX family of FPGAs is fully supported by both Libero Integrated Design Environment and Designer
FPGA Development software. Libero IDE is a design management environment that streamlines the
design flow. Libero IDE provides an integrated design manager that seamlessly integrates design tools
while guiding the user through the design flow, managing all design and log files, and passing necessary
design data among tools. Additionally, Libero IDE allows users to integrate both schematic and HDL
synthesis into a single flow and verify the entire design in a single environment. Libero IDE includes
Synplify for Microsemi from Synplicity, ViewDraw for Microsemi from Mentor Graphics, ModelSim
HDL Simulator from Mentor Graphics, WaveFormer Lite from SynaptiCAD, and Designer software
from Microsemi. Refer to the Libero IDE flow (located on Microsemi SoC Product Group’s website)
diagram for more information.
Table 1-8 Device Configuration Options for Probe Capability (TRST pin reserved)
JTAG Mode
TRST1
Security Fuse
Programmed
PRA, PRB2
TDI, TCK, TDO2
Dedicated
LOW
No
User I/O3
Probing Unavailable
Flexible
LOW
No
User I/O3
Dedicated
HIGH
No
Probe Circuit Outputs
Probe Circuit Inputs
Flexible
HIGH
No
Probe Circuit Outputs
Probe Circuit Inputs
–
Yes
Probe Circuit Secured
Notes:
1. If TRST pin is not reserved, the device behaves according to TRST = HIGH in the table.
2. Avoid using the TDI, TCK, TDO, PRA, and PRB pins as input or bidirectional ports. Since these pins are active during
probing, input signals will not pass through these pins and may cause contention.
3. If no user signal is assigned to these pins, they will behave as unused I/Os in this mode. Unused pins are automatically
tristated by Microsemi Designer software.
Figure 1-13 Silicon Explorer II Probe Setup
Serial
Connection
Additional 16 Channels
(Logic Analyzer)
Silicon Explorer II
TDI
TCK
TMS
16 Pin
Connection
22 Pin
Connection
PRA
PRB
TDO
eX FPGAs
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