Revision 10 1-27 eX Family Timing Characteristics Table 1-17 eX Family Timing Characteristics (Worst-Case" />
參數(shù)資料
型號： EX64-TQG64I
廠商： Microsemi SoC
文件頁數(shù)： 25/48頁
文件大?。?/td> 0K
描述： IC FPGA ANTIFUSE 3K 64-TQFP
標(biāo)準(zhǔn)包裝： 160
系列： EX
邏輯元件/單元數(shù)： 128
輸入/輸出數(shù)： 41
門數(shù)： 3000
電源電壓： 2.3 V ~ 2.7 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 85°C
封裝/外殼： 64-LQFP
供應(yīng)商設(shè)備封裝： 64-TQFP（10x10）
eX Family FPGAs
Revision 10
1-27
eX Family Timing Characteristics
Table 1-17 eX Family Timing Characteristics
(Worst-Case Commercial Conditions, VCCA = 2.3 V, TJ = 70C)
–P Speed
Std Speed
–F Speed
Units
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
C-Cell Propagation Delays1
tPD
Internal Array Module
0.7
1.0
1.4
ns
Predicted Routing Delays2
tDC
FO=1 Routing Delay, DirectConnect
0.1
0.2
ns
tFC
FO=1 Routing Delay, FastConnect
0.3
0.5
0.7
ns
tRD1
FO=1 Routing Delay
0.3
0.5
0.7
ns
tRD2
FO=2 Routing Delay
0.4
0.6
0.8
ns
tRD3
FO=3 Routing Delay
0.5
0.8
1.1
ns
tRD4
FO=4 Routing Delay
0.7
1.0
1.3
ns
tRD8
FO=8 Routing Delay
1.2
1.7
2.4
ns
tRD12
FO=12 Routing Delay
1.7
2.5
3.5
ns
R-Cell Timing
tRCO
Sequential Clock-to-Q
0.6
0.9
1.3
ns
tCLR
Asynchronous Clear-to-Q
0.6
0.8
1.2
ns
tPRESET
Asynchronous Preset-to-Q
0.7
0.9
1.3
ns
tSUD
Flip-Flop Data Input Set-Up
0.5
0.7
1.0
ns
tHD
Flip-Flop Data Input Hold
0.0
ns
tWASYN
Asynchronous Pulse Width
1.3
1.9
2.6
ns
tRECASYN
Asynchronous Recovery Time
0.3
0.5
0.7
ns
tHASYN
Asynchronous Hold Time
0.3
0.5
0.7
ns
2.5 V Input Module Propagation Delays
tINYH
Input Data Pad-to-Y HIGH
0.6
0.9
1.3
ns
tINYL
Input Data Pad-to-Y LOW
0.8
1.1
1.5
ns
3.3 V Input Module Propagation Delays
tINYH
Input Data Pad-to-Y HIGH
0.7
1.0
1.4
ns
tINYL
Input Data Pad-to-Y LOW
0.9
1.3
1.8
ns
5.0 V Input Module Propagation Delays
tINYH
Input Data Pad-to-Y HIGH
0.7
1.0
1.4
ns
tINYL
Input Data Pad-to-Y LOW
0.9
1.3
1.8
ns
Input Module Predicted Routing Delays2
tIRD1
FO=1 Routing Delay
0.3
0.4
0.5
ns
tIRD2
FO=2 Routing Delay
0.4
0.6
0.8
ns
tIRD3
FO=3 Routing Delay
0.5
0.8
1.1
ns
tIRD4
FO=4 Routing Delay
0.7
1.0
1.3
ns
tIRD8
FO=8 Routing Delay
1.2
1.7
2.4
ns
tIRD12
FO=12 Routing Delay
1.7
2.5
3.5
ns
Notes:
1. For dual-module macros, use tPD + tRD1 + tPDn, tRCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance.
Post-route timing analysis or simulation is required to determine actual worst-case
performance.
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