1-26 Revision 10 Timing Characteristics Timing characteristics for eX devices fall into three categories:" />
參數(shù)資料
型號： EX128-TQG64A
廠商： Microsemi SoC
文件頁數(shù)： 24/48頁
文件大?。?/td> 0K
描述： IC FPGA ANTIFUSE 6K 64-TQFP
標(biāo)準(zhǔn)包裝： 160
系列： EX
邏輯元件/單元數(shù)： 256
輸入/輸出數(shù)： 46
門數(shù)： 6000
電源電壓： 2.3 V ~ 2.7 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 125°C
封裝/外殼： 64-LQFP
供應(yīng)商設(shè)備封裝： 64-TQFP（10x10）
eX FPGA Architecture and Characteristics
1-26
Revision 10
Timing Characteristics
Timing characteristics for eX devices fall into three categories: family-dependent, device-dependent, and
design-dependent. The input and output buffer characteristics are common to all eX family members.
Internal routing delays are device-dependent. Design dependency means actual delays are not
determined until after placement and routing of the user’s design are complete. Delay values may then
be determined by using the Timer utility or performing simulation with post-layout delays.
Critical Nets and Typical Nets
Propagation delays are expressed only for typical nets, which are used for initial design performance
evaluation. Critical net delays can then be applied to the most timing critical paths. Critical nets are
determined by net property assignment prior to placement and routing. Up to six percent of the nets in a
design may be designated as critical.
Long Tracks
Some nets in the design use long tracks. Long tracks are special routing resources that span multiple
rows, columns, or modules. Long tracks employ three to five antifuse connections. This increases
capacitance and resistance, resulting in longer net delays for macros connected to long tracks. Typically,
no more than six percent of nets in a fully utilized device require long tracks. Long tracks contribute
approximately 4 ns to 8.4 ns delay. This additional delay is represented statistically in higher fanout
routing delays.
Timing Derating
eX devices are manufactured with a CMOS process. Therefore, device performance varies according to
temperature, voltage, and process changes. Minimum timing parameters reflect maximum operating
voltage, minimum operating temperature, and best-case processing. Maximum timing parameters reflect
minimum operating voltage, maximum operating temperature, and worst-case processing.
Temperature and Voltage Derating Factors
Table 1-16 Temperature and Voltage Derating Factors
(Normalized to Worst-Case Commercial, TJ = 70C, VCCA = 2.3V)
VCCA
Junction Temperature (TJ)
–55
–40
0
25
70
85
125
2.3
0.79
0.80
0.87
0.88
1.00
1.04
1.13
2.5
0.74
0.81
0.83
0.93
0.97
1.06
2.7
0.69
0.70
0.76
0.78
0.88
0.91
1.00
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EX128-TQG64I 功能描述:IC FPGA ANTIFUSE 6K 64-TQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:EX 標(biāo)準(zhǔn)包裝:152 系列:IGLOO PLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):792 RAM 位總計(jì):- 輸入/輸出數(shù):120 門數(shù):30000 電源電壓:1.14 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 85°C 封裝/外殼:289-TFBGA，CSBGA 供應(yīng)商設(shè)備封裝:289-CSP（14x14）
EX12BTQ64I 制造商:ACTEL 功能描述:New
EX12L-120PC/3E-GL/L 制造商:Hirose 功能描述:
EX12L-120PC/3E-GL/L(50) 功能描述:集管和線殼 HIROSE ELECTRIC RoHS:否 產(chǎn)品種類:1.0MM Rectangular Connectors 產(chǎn)品類型:Headers - Pin Strip 系列:DF50 觸點(diǎn)類型:Pin (Male) 節(jié)距:1 mm 位置/觸點(diǎn)數(shù)量:16 排數(shù):1 安裝風(fēng)格:SMD/SMT 安裝角:Right 端接類型:Solder 外殼材料:Liquid Crystal Polymer (LCP) 觸點(diǎn)材料:Brass 觸點(diǎn)電鍍:Gold 制造商:Hirose Connector
EX12L-120PC/3E-GL/L(51) 功能描述:集管和線殼 HIROSE ELECTRIC RoHS:否 產(chǎn)品種類:1.0MM Rectangular Connectors 產(chǎn)品類型:Headers - Pin Strip 系列:DF50 觸點(diǎn)類型:Pin (Male) 節(jié)距:1 mm 位置/觸點(diǎn)數(shù)量:16 排數(shù):1 安裝風(fēng)格:SMD/SMT 安裝角:Right 端接類型:Solder 外殼材料:Liquid Crystal Polymer (LCP) 觸點(diǎn)材料:Brass 觸點(diǎn)電鍍:Gold 制造商:Hirose Connector
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