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REV.
–47–
ADuC812
12 MHz
Variable Clock
Parameter
Min
Max
Min
Max
Unit
EXTERNAL PROGRAM MEMORY READ CYCLE
tLHLL
ALE Pulsewidth
127
2tCK –40
ns
tAVLL
Address Valid to ALE Low
43
tCK –40
ns
tLLAX
Address Hold after ALE Low
53
tCK –30
ns
tLLIV
ALE Low to Valid Instruction In
234
4tCK – 100
ns
tLLPL
ALE Low to
PSEN Low
53
tCK –30
ns
tPLPH
PSEN Pulsewidth
205
3tCK –45
ns
tPLIV
PSEN Low to Valid Instruction In
145
3tCK – 105
ns
tPXIX
Input Instruction Hold after
PSEN
00
ns
tPXIZ
Input Instruction Float after
PSEN
59
tCK –25
ns
tAVIV
Address to Valid Instruction In
312
5tCK – 105
ns
tPLAZ
PSEN Low to Address Float
25
ns
tPHAX
Address Hold after
PSEN High
0
ns
MCLK
ALE (O)
PSEN (O)
PORT 0 (I/O)
PORT 2 (O)
tLHLL
tAVLL
tLLPL
tPLPH
tLLIV
tPLIV
tPLAZ
tLLAX
tPXIX
tPXIZ
tPHAX
tAVIV
PCL (OUT)
INSTRUCTION
(IN)
PCH
Figure 51. External Program Memory Read Cycle
F