參數(shù)資料
型號(hào)： EVAL-ADUC812QSZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 17/57頁(yè)
文件大?。?/td> 0K
描述： BOARD EVALUATION FOR ADUC812
產(chǎn)品培訓(xùn)模塊： Process Control
標(biāo)準(zhǔn)包裝： 1
系列： QuickStart™ 套件
類(lèi)型： MCU
適用于相關(guān)產(chǎn)品： ADuC812
所含物品： 評(píng)估板、電源、纜線、軟件和說(shuō)明文檔
REV.
ADuC812
–24–
WATCHDOG TIMER
The purpose of the watchdog timer is to generate a device reset
within a reasonable amount of time if the ADuC812 enters an
erroneous state, possibly due to a programming error. The Watch-
dog function can be disabled by clearing the WDE (Watchdog
Enable) bit in the Watchdog Control (WDCON) SFR. When
enabled, the watchdog circuit will generate a system reset if the
user program fails to set the watchdog timer refresh bits (WDR1,
WDR2) within a predetermined amount of time (see PRE2–0
bits in WDCON). The watchdog timer itself is a 16-bit counter.
The watchdog timeout interval can be adjusted via the PRE2–0 bits
in WDCON. Full Control and Status of the watchdog timer function
can be controlled via the watchdog timer control SFR (WDCON).
2
E
R
P1
E
R
P0
E
R
P—
1
R
D
W2
R
D
WS
D
WE
D
W
Table IX. WDCON SFR Bit Designations
Bit
Name
Description
7
PRE2
Watchdog Timer Prescale Bits.
6
PRE1
5
PRE0
PRE2
PRE1
PRE0
Timeout Period (ms)
000
16
001
32
010
64
011
128
100
256
101
512
1
0
1024
1
2048
4
—
Not Used.
3
WDR1
Watchdog Timer Refresh Bits. Set sequentially to refresh the watchdog timer.
2
WDR2
1
WDS
Watchdog Status Bit.
Set by the Watchdog Controller to indicate that a watchdog timeout has occurred.
Cleared by writing a “0” or by an external hardware reset. It is not cleared by a watchdog reset.
0
WDE
Watchdog Enable Bit.
Set by user to enable the watchdog and clear its counters.
Watchdog Timer
WDCON
Control Register
SFR Address
C0H
Power-On Default Value
00H
Bit Addressable
Yes
Example
To set up the watchdog timer for a timeout period of 2048 ms,
the following code would be used:
MOV
WDCON,#0E0h
;2.048 second
;timeout period
SETB
WDE
;enable watchdog timer
To prevent the watchdog timer from timing out, the timer
refresh bits need to be set before 2.048 seconds has elapsed.
SETB
WDR1
;refresh watchdog timer..
SETB
WDR2
; ..bits must be set in this
;order
POWER SUPPLY MONITOR
As its name suggests, the Power Supply Monitor, once enabled,
monitors both supplies (AVDD and DVDD) on the ADuC812. It
will indicate when either power supply drops below one of five
user selectable voltage trip points from 2.63 V to 4.63 V. For
correct operation of the Power Supply Monitor function, AVDD
must be equal to or greater than 2.7 V. The Power Supply
Monitor function is controlled via the PSMCON SFR. If
enabled via the IE2 SFR, the Power Supply Monitor will interrupt
the core using the PSMI bit in the PSMCON SFR. This bit will
not be cleared until the failing power supply has returned
above the trip point for at least 256 ms. This ensures that the
power supply has fully settled before the bit is cleared. This
monitor function allows the user to save working registers to avoid
possible data loss due to the low supply condition, and also ensures
that normal code execution will not resume until a safe supply
level has been well established. The supply monitor is also
protected against spurious glitches triggering the interrupt circuit.
F
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