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| 型號： | EVAL-ADUC7024QSZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 89/104頁 |
| 文件大小： | 0K |
| 描述： | KIT DEV QUICK START ADUC7024 |
| 產(chǎn)品培訓(xùn)模塊： | ARM7 Applications & Tools Intro to ARM7 Core & Microconverters |
| 設(shè)計資源： | ADUC7024 Dev System Schematic/Brd Outline 7024 Gerber Files |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | QuickStart™ 套件 |
| 類型： | MCU |
| 適用于相關(guān)產(chǎn)品： | ADuC7024 |
| 所含物品： | 評估板、電源、纜線、軟件和說明文檔 |
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Data Sheet
ADuC7019/20/21/22/24/25/26/27/28/29
Rev. F | Page 85 of 104
In normal mode, an IRQ is generated each time the value of the
counter reaches zero when counting down. It is also generated
each time the counter value reaches full scale when counting
up. An IRQ can be cleared by writing any value to clear the
register of that particular timer (TxCLRI).
When using an asynchronous clock-to-clock timer, the
interrupt in the timer block may take more time to clear
than the time it takes for the code in the interrupt routine to
execute. Ensure that the interrupt signal is cleared before
leaving the interrupt service routine. This can be done by
checking the IRQSTA MMR.
Hour:Minute:Second:1/128 Format
To use the timer in hour:minute:second:hundredths format,
select the 32,768 kHz clock and prescaler of 256. The hun-
dredths field does not represent milliseconds but 1/128 of
a second (256/32,768). The bits representing the hour,
minute, and second are not consecutive in the register.
This arrangement applies to TxLD and TxVAL when using
the hour:minute:second:hundredths format as set in
TxCON[5:4]. See Table 171 for additional details.
Table 171. Hour:Minnute:Second:Hundredths Format
Bit
Value
Description
31:24
0 to 23 or 0 to 255
Hours
23:22
0
Reserved
21:16
0 to 59
Minutes
15:14
0
Reserved
13.8
0 to 59
Seconds
7
0
Reserved
6:0
0 to 127
1/128 second
Timer0 (RTOS Timer)
Timer0 is a general-purpose, 16-bit timer (count down) with a
programmable prescaler (see Figure 77). The prescaler source is
the core clock frequency (HCLK) and can be scaled by factors
of 1, 16, or 256.
Timer0 can be used to start ADC conversions as shown in the
block diagram in Figure 77.
04955-
034
16-BIT
LOAD
TIMER0
VALUE
16-BIT
DOWN
COUNTER
PRESCALER
/1, 16 OR 256
HCLK
TIMER0 IRQ
ADC CONVERSION
Figure 77. Timer0 Block Diagram
The Timer0 interface consists of four MMRs: T0LD, T0VAL,
T0CON, and T0CLRI.
Table 172. T0LD Register
Name
Address
Default Value
Access
T0LD
0xFFFF0300
0x0000
R/W
T0LD is a 16-bit load register.
Table 173. T0VAL Register
Name
Address
Default Value
Access
T0VAL
0xFFFF0304
0xFFFF
R
T0VAL is a 16-bit read-only register representing the current
state of the counter.
Table 174. T0CON Register
Name
Address
Default Value
Access
T0CON
0xFFFF0308
0x0000
R/W
T0CON is the configuration MMR described in Table 175.
Table 175. T0CON MMR Bit Descriptions
Bit
Value
Description
15:8
Reserved.
7
Timer0 enable bit. Set by user to enable Timer0.
Cleared by user to disable Timer0 by default.
6
Timer0 mode. Set by user to operate in
periodic mode. Cleared by user to operate
in free-running mode. Default mode.
5:4
Reserved.
3:2
Prescale.
00
Core Clock/1. Default value.
01
Core Clock/16.
10
Core Clock/256.
11
Undefined. Equivalent to 00.
1:0
Reserved.
Table 176. T0CLRI Register
Name
Address
Default Value
Access
T0CLRI
0xFFFF030C
0xFF
W
T0CLRI is an 8-bit register. Writing any value to this register
clears the interrupt.
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