參數(shù)資料
型號： EVAL-ADUC7024QSZ
廠商： Analog Devices Inc
文件頁數(shù)： 48/104頁
文件大?。?/td> 0K
描述： KIT DEV QUICK START ADUC7024
產(chǎn)品培訓模塊： ARM7 Applications & Tools
Intro to ARM7 Core & Microconverters
設(shè)計資源： ADUC7024 Dev System Schematic/Brd Outline
7024 Gerber Files
標準包裝： 1
系列： QuickStart™ 套件
類型： MCU
適用于相關(guān)產(chǎn)品： ADuC7024
所含物品： 評估板、電源、纜線、軟件和說明文檔
ADuC7019/20/21/22/24/25/26/27/28/29
Data Sheet
Rev. F | Page 48 of 104
Table 22. ADCCN MMR Bit Designation
Bit
Value
Description
7:5
Reserved.
4:0
Negative channel selection bits.
00000
ADC0.
00001
ADC1.
00010
ADC2.
00011
ADC3.
00100
ADC4.
00101
ADC5.
00110
ADC6.
00111
ADC7.
01000
ADC8.
01001
ADC9.
01010
ADC10.
01011
ADC11.
01100
DAC0/ADC12.
01101
DAC1/ADC13.
01110
DAC2/ADC14.
01111
DAC3/ADC15.
10000
Internal reference (self-diagnostic feature).
Others
Reserved.
Table 23. ADCSTA Register
Name
Address
Default Value
Access
ADCSTA
0xFFFF050C
0x00
R
ADCSTA is an ADC status register that indicates when an ADC
conversion result is ready. The ADCSTA register contains only
one bit, ADCReady (Bit 0), representing the status of the ADC.
This bit is set at the end of an ADC conversion, generating an
ADC interrupt. It is cleared automatically by reading the
ADCDAT MMR. When the ADC is performing a conversion,
the status of the ADC can be read externally via the ADCBUSY
pin. This pin is high during a conversion. When the conversion
is finished, ADCBUSY goes back low. This information can be
available on P0.5 (see the General-Purpose Input/Output
section) if enabled in the ADCCON register.
Table 24. ADCDAT Register
Name
Address
Default Value
Access
ADCDAT
0xFFFF0510
0x00000000
R
ADCDAT is an ADC data result register. It holds the 12-bit
ADC result as shown in Figure 51.
Table 25. ADCRST Register
Name
Address
Default Value
Access
ADCRST
0xFFFF0514
0x00
R/W
ADCRST resets the digital interface of the ADC. Writing any value
to this register resets all the ADC registers to their default values.
Table 26. ADCGN Register
Name
Address
Default Value
Access
ADCGN
0xFFFF0530
0x0200
R/W
ADCGN is a 10-bit gain calibration register.
Table 27. ADCOF Register
Name
Address
Default Value
Access
ADCOF
0xFFFF0534
0x0200
R/W
ADCOF is a 10-bit offset calibration register.
CONVERTER OPERATION
The ADC incorporates a successive approximation (SAR)
architecture involving a charge-sampled input stage. This
architecture can operate in three modes: differential, pseudo
differential, and single-ended.
Differential Mode
The ADuC7019/20/21/22/24/25/26/27/28/29 each contain a
successive approximation ADC based on two capacitive DACs.
Figure 54 and Figure 55 show simplified schematics of the ADC
in acquisition and conversion phase, respectively. The ADC
comprises control logic, a SAR, and two capacitive DACs. In
Figure 54 (the acquisition phase), SW3 is closed and SW1 and
SW2 are in Position A. The comparator is held in a balanced
condition, and the sampling capacitor arrays acquire the
differential signal on the input.
04955-
017
CAPACITIVE
DAC
CAPACITIVE
DAC
CONTROL
LOGIC
COMPARATOR
SW3
SW1
A
B
SW2
CS
VREF
AIN0
AIN11
MUX
CHANNEL+
CHANNEL–
Figure 54. ADC Acquisition Phase
When the ADC starts a conversion, as shown in Figure 55, SW3
opens, and then SW1 and SW2 move to Position B. This causes
the comparator to become unbalanced. Both inputs are discon-
nected once the conversion begins. The control logic and the
charge redistribution DACs are used to add and subtract fixed
amounts of charge from the sampling capacitor arrays to bring
the comparator back into a balanced condition. When the
comparator is rebalanced, the conversion is complete. The
control logic generates the ADC output code. The output
impedances of the sources driving the VIN+ and VIN– input
voltage pins must be matched; otherwise, the two inputs have
different settling times, resulting in errors.
04955-
018
CAPACITIVE
DAC
CAPACITIVE
DAC
CONTROL
LOGIC
COMPARATOR
SW3
SW1
A
B
SW2
CS
VREF
AIN0
AIN11
MUX
CHANNEL+
CHANNEL–
Figure 55. ADC Conversion Phase
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