參數(shù)資料
型號(hào)： EVAL-ADUC7024QSZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 57/104頁(yè)
文件大?。?/td> 0K
描述： KIT DEV QUICK START ADUC7024
產(chǎn)品培訓(xùn)模塊： ARM7 Applications & Tools
Intro to ARM7 Core & Microconverters
設(shè)計(jì)資源： ADUC7024 Dev System Schematic/Brd Outline
7024 Gerber Files
標(biāo)準(zhǔn)包裝： 1
系列： QuickStart™ 套件
類型： MCU
適用于相關(guān)產(chǎn)品： ADuC7024
所含物品： 評(píng)估板、電源、纜線、軟件和說(shuō)明文檔
ADuC7019/20/21/22/24/25/26/27/28/29
Data Sheet
Rev. F | Page 56 of 104
OTHER ANALOG PERIPHERALS
DAC
The ADuC7019/20/21/22/24/25/26/27/28/29 incorporate two,
three, or four 12-bit voltage output DACs on-chip, depending on
the model. Each DAC has a rail-to-rail voltage output buffer
capable of driving 5 kΩ/100 pF.
Each DAC has three selectable ranges: 0 V to VREF (internal
band gap 2.5 V reference), 0 V to DACREF, and 0 V to AVDD.
DACREF is equivalent to an external reference for the DAC.
The signal range is 0 V to AVDD.
MMRs Interface
Each DAC is independently configurable through a control
register and a data register. These two registers are identical for
the four DACs. Only DAC0CON (see Table 50) and DAC0DAT
(see Table 52) are described in detail in this section.
Table 49. DACxCON Registers
Name
Address
Default Value
Access
DAC0CON
0xFFFF0600
0x00
R/W
DAC1CON
0xFFFF0608
0x00
R/W
DAC2CON
0xFFFF0610
0x00
R/W
DAC3CON
0xFFFF0618
0x00
R/W
Table 50. DAC0CON MMR Bit Designations
Bit
Name
Value
Description
7:6
Reserved.
5
DACCLK
DAC update rate. Set by user to
update the DAC using Timer1.
Cleared by user to update the DAC
using HCLK (core clock).
4
DACCLR
DAC clear bit. Set by user to enable
normal DAC operation. Cleared by
user to reset data register of the DAC
to 0.
3
Reserved. This bit should be left at 0.
2
Reserved. This bit should be left at 0.
1:0
DAC range bits.
00
Power-down mode. The DAC output is
in three-state.
01
0 V to DACREF range.
10
0 V to VREF (2.5 V) range.
11
0 V to AVDD range.
Table 51. DACxDAT Registers
Name
Address
Default Value
Access
DAC0DAT
0xFFFF0604
0x00000000
R/W
DAC1DAT
0xFFFF060C
0x00000000
R/W
DAC2DAT
0xFFFF0614
0x00000000
R/W
DAC3DAT
0xFFFF061C
0x00000000
R/W
Table 52. DAC0DAT MMR Bit Designations
Bit
Description
31:28
Reserved.
27:16
12-bit data for DAC0.
15:0
Reserved.
Using the DACs
The on-chip DAC architecture consists of a resistor string DAC
followed by an output buffer amplifier. The functional equivalent
is shown in Figure 63.
04
95
5-
0
23
R
DAC0
VREF
AVDD
DACREF
Figure 63. DAC Structure
As illustrated in Figure 63, the reference source for each DAC is
user-selectable in software. It can be AVDD, VREF, or DACREF. In
0-to-AVDD mode, the DAC output transfer function spans from
0 V to the voltage at the AVDD pin. In 0-to-DACREF mode, the
DAC output transfer function spans from 0 V to the voltage at the
DACREF pin. In 0-to-VREF mode, the DAC output transfer function
spans from 0 V to the internal 2.5 V reference, VREF.
The DAC output buffer amplifier features a true, rail-to-rail
output stage implementation. This means that when unloaded,
each output is capable of swinging to within less than 5 mV of
both AVDD and ground. Moreover, the DAC’s linearity specification
(when driving a 5 kΩ resistive load to ground) is guaranteed
through the full transfer function, except Code 0 to Code 100,
and, in 0-to-AVDD mode only, Code 3995 to Code 4095.
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