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參數(shù)資料
| 型號(hào)： | EVAL-ADAU1761Z |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 39/92頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR ADAU1761 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | SigmaDSP® |
| 主要目的： | 音頻編解碼器 |
| 嵌入式： | 是，DSP |
| 已用 IC / 零件： | ADAU1761 |
| 主要屬性： | 立體聲，24 位，8 ~ 96 kHz 采樣率，GUI 工具 |
| 次要屬性： | I²C 和 GPIO 接口，2 差分和 1 個(gè)立體聲單端模擬輸入和輸出 |
| 已供物品： | 2 個(gè)板，線纜，CD |
| 產(chǎn)品目錄頁(yè)面： | 776 (CN2011-ZH PDF) |
| 相關(guān)產(chǎn)品： | ADAU1761BCPZ-RL-ND - IC SIGMADSP CODEC PLL 32LFCSP ADAU1761BCPZ-R7-ND - IC SIGMADSP CODEC PLL 32LFCSP ADAU1761BCPZ-ND - IC SIGMADSP CODEC PLL 32LFCSP |
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ADAU1761
Rev. C | Page 44 of 92
APPLICATIONS INFORMATION
POWER SUPPLY BYPASS CAPACITORS
Each analog and digital power supply pin should be bypassed to
its nearest appropriate ground pin with a single 100 nF capaci-
tor. The connections to each side of the capacitor should be as
short as possible, and the trace should stay on a single layer with
no vias. For maximum effectiveness, locate the capacitor equi-
distant from the power and ground pins or, when equidistant
placement is not possible, slightly closer to the power pin.
Thermal connections to the ground planes should be made
on the far side of the capacitor.
Each supply signal on the board should also be bypassed with a
single bulk capacitor (10 μF to 47 μF).
VDD
GND
TO GND
TO VDD
CAPACITOR
07
68
0-
0
48
Figure 63. Recommended Power Supply Bypass Capacitor Layout
GSM NOISE FILTER
In mobile phone applications, excessive 217 Hz GSM noise on
the analog supply pins can degrade the audio quality. To avoid
this problem, it is recommended that an L-C filter be used in
series with the bypass capacitors for the AVDD pins. This filter
should consist of a 1.2 nH inductor and a 9.1 pF capacitor in
series between AVDD and ground, as shown in Figure 64.
AVDD
0.1F
9.1pF
1.2nH
10F
+
0
76
80
-0
49
Figure 64. GSM Filter on the Analog Supply Pins
GROUNDING
A single ground plane should be used in the application layout.
Components in an analog signal path should be placed away
from digital signals.
EXPOSED PAD PCB DESIGN
The ADAU1761 has an exposed pad on the underside of the
LFCSP. This pad is used to couple the package to the PCB for
heat dissipation when using the outputs to drive earpiece or
headphone loads. When designing a board for the ADAU1761,
special consideration should be given to the following:
A copper layer equal in size to the exposed pad should be
on all layers of the board, from top to bottom, and should
connect somewhere to a dedicated copper board layer (see
Vias should be placed to connect all layers of copper,
allowing for efficient heat and energy conductivity. For an
example, see Figure 66, which has nine vias arranged in a
3 inch × 3 inch grid in the pad area.
TOP
POWER
GROUND
BOTTOM
COPPER SQUARES
VIAS
0
76
80
-0
50
Figure 65. Exposed Pad Layout Example, Side View
07
68
0-
0
51
Figure 66. Exposed Pad Layout Example, Top View
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| EVAL-ADAU1781Z | 功能描述:BOARD EVAL FOR ADAU1781 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評(píng)估演示板和套件 系列:SigmaDSP® 標(biāo)準(zhǔn)包裝:1 系列:- 主要目的:電信，線路接口單元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要屬性:T1/J1/E1 LIU 次要屬性:- 已供物品:板，電源，線纜，CD 其它名稱:82EBV2081 |
| EVAL-ADAU1962AZ | 制造商:Analog Devices 功能描述:EVAL BOARD FOR ADAU1962A - Boxed Product (Development Kits) 制造商:Analog Devices 功能描述:Eval Board for ADAU1962A |
| EVAL-ADAU1966AZ | 制造商:Analog Devices 功能描述:EVAL BOARD FOR ADAU1962A - Boxed Product (Development Kits) |
| EVAL-ADAU1966Z | 功能描述:BOARD EVAL FOR ADAU1966 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評(píng)估板 - 數(shù)模轉(zhuǎn)換器 (DAC) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- DAC 的數(shù)量:4 位數(shù):12 采樣率（每秒）:- 數(shù)據(jù)接口:串行，SPI? 設(shè)置時(shí)間:3µs DAC 型:電流/電壓 工作溫度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581 |
| EVAL-ADAU1966Z | 制造商:Analog Devices 功能描述:ADAU1966, DAC, SIGMA DELTA, SPI, I2C, EV |
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