參數(shù)資料
型號(hào)： EVAL-ADAU1761Z
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 23/92頁(yè)
文件大?。?/td> 0K
描述： BOARD EVAL FOR ADAU1761
標(biāo)準(zhǔn)包裝： 1
系列： SigmaDSP®
主要目的： 音頻編解碼器
嵌入式： 是，DSP
已用 IC / 零件： ADAU1761
主要屬性： 立體聲，24 位，8 ~ 96 kHz 采樣率，GUI 工具
次要屬性： I²C 和 GPIO 接口，2 差分和 1 個(gè)立體聲單端模擬輸入和輸出
已供物品： 2 個(gè)板，線(xiàn)纜，CD
產(chǎn)品目錄頁(yè)面： 776 (CN2011-ZH PDF)
相關(guān)產(chǎn)品： ADAU1761BCPZ-RL-ND - IC SIGMADSP CODEC PLL 32LFCSP
ADAU1761BCPZ-R7-ND - IC SIGMADSP CODEC PLL 32LFCSP
ADAU1761BCPZ-ND - IC SIGMADSP CODEC PLL 32LFCSP
ADAU1761
Rev. C | Page 3 of 92
REVISION HISTORY
9/10—Rev. B to Rev. C
Changes to Figure 1...........................................................................1
5/10—Rev. A to Rev. B
Changes to Burst Mode Writing and Reading Section ..............38
Changes to Table 33 ........................................................................51
Added R67: Dejitter Control, 16,438 (0x4036) Section .............79
12/09—Rev. 0 to Rev. A
Changes to Features Section ............................................................1
Change to General Description Section.........................................1
Changes to Table 1 ............................................................................6
Change to Table 5 ............................................................................10
Changes to Figure 6.........................................................................13
Changes to Table 10 ........................................................................15
Changes to Captions of Figure 15, Figure 16, Figure 18, and
Figure 19 ...........................................................................................18
Changes to Captions of Figure 21 and Figure 24 ........................19
Added Figure 25; Renumbered Sequentially ...............................19
Change to Figure 26 ........................................................................20
Change to Figure 27 ........................................................................21
Change to Figure 28 ........................................................................22
Change to Theory of Operation Section ......................................23
Changes to Power Reduction Modes Section and
Case 1: PLL Is Bypassed Section ...................................................24
Changes to PLL Lock Acquisition Section...................................25
Changes to Core Clock Section and Figure 30............................26
Change to Sampling Rates Section................................................27
Changes to Input Signal Paths Section and Figure 32................29
Changes to Figure 33 and Figure 34 .............................................30
Changes to ADC Full-Scale Level Section ...................................31
Change to Automatic Level Control (ALC) Section...................32
Changes to Output Signal Paths Section......................................35
Changes to Headphone Output Section.......................................36
Changes to Jack Detection Section, Pop-and-Click
Suppression Section, and Line Outputs Section .........................37
Changes to Control Ports Section and I2C Port Section ............38
Added Burst Mode Writing and Reading Section ......................38
Changes to SPI Port Section ..........................................................41
Changes to Serial Data Input/Output Ports Section
and Table 25 .....................................................................................42
Added Figure 57 ..............................................................................42
Changes to Architecture Section and Figure 67..........................45
Added Startup Section....................................................................45
Changes to Parameter RAM Section and Data RAM Section ..47
Changes to Table 33 ........................................................................51
Changes to R2: Digital Microphone/Jack Detection Control,
16,392 (0x4008) Section and Table 36..........................................54
Changes to Table 42 ........................................................................58
Changes to Table 43 ........................................................................59
Changes to R15: Serial Port Control 0, 16,405 (0x4015)
Section and Table 49 .......................................................................63
Change to Table 50..........................................................................64
Changes to Table 51, R18: Converter Control 1, 16,408
(0x4018) Section, and Table 52 .....................................................65
Changes to Table 60, R27: Playback L/R Mixer Right (Mixer 6)
Line Output Control, 16,417 (0x4021) Section, and Table 61...71
Changes to Table 62, R29: Playback Headphone Left Volume
Control, 16,419 (0x4023) Section, and Table 63 .........................72
Changes to Table 64 ........................................................................73
Changes to R42: Jack Detect Pin Control, 16,433 (0x4031)
Section and Table 76 .......................................................................79
Changes to R57: DSP Sampling Rate Setting, 16,619 (0x40EB)
Section and Table 81 .......................................................................81
Change to Table 85..........................................................................83
Change to Table 88..........................................................................84
Changes to R66: Clock Enable 1, 16,634 (0x40FA) Section
and Table 90 .....................................................................................85
1/09—Revision 0: Initial Version
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