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| 型號： | EVAL-ADAU1701MINIZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 6/53頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL SIGMADSP AUD ADAU1701 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | SigmaDSP® |
| 類型： | DSP：音頻 |
| 適用于相關(guān)產(chǎn)品： | ADAU1701 |
| 所含物品： | 板，線纜 |
| 產(chǎn)品目錄頁面： | 776 (CN2011-ZH PDF) |
| 相關(guān)產(chǎn)品： | ADAU1701JSTZ-RL-ND - IC AUDIO PROC 2ADC/4DAC 48-LQFP ADAU1701JSTZ-ND - IC AUDIO PROC 2ADC/4DAC 48-LQFP |
| 其它名稱： | ADAU1701MINIBZ ADAU1701MINIBZ-ND ADAU1701MINIZ ADAU1701MINIZ-ND |
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ADAU1701
Rev. B | Page 13 of 52
Pin No.
Mnemonic
Type1
Description
33
PGND
PWR
PLL Ground Pin. The AGND, DGND, and PGND pins can be tied directly together in a
common ground plane. Decouple PGND to PVDD by using a 100 nF capacitor.
34
PVDD
PWR
3.3 V Power Supply for the PLL and the Auxiliary ADC Analog Section. Decouple this pin to
PGND by using a 100 nF capacitor.
35
PLL_LF
A_OUT
PLL Loop Filter Connection. Two capacitors and a resistor need to be connected to this pin, as
shown in Figure 15. See the Setting Master Clock/PLL Mode section for more details.
36, 48
AVDD
PWR
3.3 V Analog Supply. Decouple this pin to AGND by using a 100 nF capacitor.
38, 39
PLL_MODE0,
PLL_MODE1
D_IN
PLL Mode Setting. PLL_MODE0 and PLL_MODE1 set the output frequency of the master
clock PLL. See the Setting Master Clock/PLL Mode section for more details.
40
CM
A_OUT
1.5 V Common-Mode Reference. Connect a 47 μF decoupling capacitor between this pin and
ground to reduce crosstalk between the ADCs and DACs. The material of the capacitors is not
critical. This pin can be used to bias external analog circuits, as long as those circuits are not
drawing current from the pin (such as when CM is connected to the noninverting input of
an op amp).
41
FILTD
A_OUT
DAC Filter Decoupling Pin. Connect a 10 μF capacitor between this pin and ground. The
capacitor material is not critical. The voltage on this pin is 1.5 V.
43 to 46
VOUT3
A_OUT
VOUT DAC Output. The full-scale output voltage is 0.9 V rms. This output can be used with
either an active or passive output reconstruction filter. See the Audio DACs section for details.
44
VOUT2
A_OUT
VOUT2 DAC Output. The full-scale output voltage is 0.9 V rms. This output can be used with
either an active or passive output reconstruction filter. See the Audio DACs section for details.
45
VOUT1
A_OUT
VOUT1 DAC Output. The full-scale output voltage is 0.9 V rms. This output can be used with
either an active or passive output reconstruction filter. See the Audio DACs section for details.
46
VOUT0
A_OUT
VOUT0 DAC Output. The full-scale output voltage is 0.9 V rms. This output can be used with
either an active or passive output reconstruction filter. See the Audio DACs section for details.
47
FILTA
A_OUT
ADC Filter Decoupling Pin. A 10 μF capacitor should be connected between this pin and
ground. The capacitor material is not critical. The voltage on this pin is 1.5 V.
1 PWR = power/ground, A_IN = analog input, D_IN = digital input, A_OUT = analog output, D_IO = digital input/output, D_IO/A_IO = digital input/output or analog
input/output.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EVAL-ADAU1701MINIZ | 制造商:Analog Devices 功能描述:ADAU1701MINIZ EvaluationBoard |
| EVAL-ADAU1702EB | 制造商:AD 制造商全稱:Analog Devices 功能描述:SigmaDSP 28-56-Bit Audio Processor with Two ADCs and Four DACs |
| EVAL-ADAU1702EBZ | 制造商:Analog Devices 功能描述:EVALBRD SIGMADSP28/56-B AUDIOPR2ADC/4DAC - Bulk |
| EVAL-ADAU1761Z | 功能描述:BOARD EVAL FOR ADAU1761 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:SigmaDSP® 標(biāo)準(zhǔn)包裝:1 系列:PSoC® 主要目的:電源管理，熱管理 嵌入式:- 已用 IC / 零件:- 主要屬性:- 次要屬性:- 已供物品:板，CD，電源 |
| EVAL-ADAU1781Z | 功能描述:BOARD EVAL FOR ADAU1781 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:SigmaDSP® 標(biāo)準(zhǔn)包裝:1 系列:- 主要目的:電信，線路接口單元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要屬性:T1/J1/E1 LIU 次要屬性:- 已供物品:板，電源，線纜，CD 其它名稱:82EBV2081 |
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