參數(shù)資料
型號(hào)： EVAL-ADAU1701MINIZ
廠(chǎng)商： Analog Devices Inc
文件頁(yè)數(shù)： 11/53頁(yè)
文件大?。?/td> 0K
描述： BOARD EVAL SIGMADSP AUD ADAU1701
標(biāo)準(zhǔn)包裝： 1
系列： SigmaDSP®
類(lèi)型： DSP：音頻
適用于相關(guān)產(chǎn)品： ADAU1701
所含物品： 板，線(xiàn)纜
產(chǎn)品目錄頁(yè)面： 776 (CN2011-ZH PDF)
相關(guān)產(chǎn)品： ADAU1701JSTZ-RL-ND - IC AUDIO PROC 2ADC/4DAC 48-LQFP
ADAU1701JSTZ-ND - IC AUDIO PROC 2ADC/4DAC 48-LQFP
其它名稱(chēng)： ADAU1701MINIBZ
ADAU1701MINIBZ-ND
ADAU1701MINIZ
ADAU1701MINIZ-ND
ADAU1701
Rev. B | Page 18 of 52
in this register. The ADC power-down mode powers down both
ADCs, and each DAC can be powered down individually. The
current savings is about 15 mA when the ADCs are powered
down and about 4 mA for each DAC that is powered down.
The voltage reference, which is supplied to both the ADCs
and DACs, should only be powered down if all ADCs and
DACs are powered down. The reference is powered down
by setting both Bit 6 and Bit 7 of the control register.
USING THE OSCILLATOR
The ADAU1701 can use an on-board oscillator to generate its
master clock. The oscillator is designed to work with a 256 × fS
master clock, which is 12.288 MHz for a fS of 48 kHz and
11.2896 MHz for a fS of 44.1 kHz. The crystal in the oscillator
circuit should be an AT-cut, parallel resonator operating at its
fundamental frequency. Figure 14 shows the external circuit
recommended for proper operation.
C1
100
MCLKI
OSCO
C2
ADAU1701
06
41
2-
01
4
Figure 14. Crystal Oscillator Circuit
The 100 Ω damping resistor on OSCO gives the oscillator a
voltage swing of approximately 2.2 V. The crystal shunt capaci-
tance should be 7 pF. Its load capacitance should be about 18 pF,
although the circuit supports values of up to 25 pF. The necessary
values of the C1 and C2 load capacitors can be calculated from
the crystal load capacitance as follows:
stray
L
C
C2
C1
C2
C1
C
+
×
=
where Cstray is the stray capacitance in the circuit and is usually
assumed to be approximately 2 pF to 5 pF.
OSCO should not be used to directly drive the crystal signal to
another IC. This signal is an analog sine wave, and it is not appro-
priate to use it to drive a digital input. There are two options for
using the ADAU1701 to provide a master clock to other ICs in
the system. The first, and less recommended, method is to use a
high impedance input digital buffer on the OSCO signal. If this
is done, minimize the trace length to the buffer input. The second
method is to use a clock from the serial output port. Pin MP11 can
be set as an output (master) clock divided down from the internal
core clock. If this pin is set to serial output port (OUTPUT_BCLK)
mode in the multipurpose pin configuration register (2081) and
the port is set to master in the serial output control register (2078),
the desired output frequency can also be set in the serial output
control register with Bits[OBF<1:0>] (see Table 48).
If the oscillator is not utilized in the design, it can be powered
down to save power. This can be done if a system master clock
is already available in the system. By default, the oscillator is
powered on. The oscillator powers down when a 1 is written to
the OPD bit of the oscillator power-down register (see Table 59).
SETTING MASTER CLOCK/PLL MODE
The MCLKI input of the ADAU1701 feeds a PLL, which generates
the 50 MIPS SigmaDSP core clock. In normal operation, the
input to MCLKI must be one of the following: 64 × fS, 256 × fS,
384 × fS, or 512 × fS, where fS is the input sampling rate. The
mode is set on PLL_MODE0 and PLL_MODE1 as described in
Table 12. If the ADAU1701 is set to receive double-rate signals
(by reducing the number of program steps per sample by a factor
of 2 using the core control register), the master clock frequency
must be 32 × fS, 128 × fS, 192 × fS, or 256 × fS. If the ADAU1701
is set to receive quad-rate signals (by reducing the number of
program steps per sample by a factor of 4 using the core control
register), the master clock frequency must be 16 × fS, 64 × fS, 96 × fS,
or 128 × fS. On power-up, a clock signal must be present on the
MCLKI pin so that the ADAU1701 can complete its
initialization routine.
Table 12. PLL Modes
MCLKI Input
PLL_MODE0
PLL_MODE1
64 × fS
0
256 × fS
0
1
384 × fS
1
0
512 × fS
1
The clock mode should not be changed without also resetting
the ADAU1701. If the mode is changed during operation, a
click or pop can result in the output signals. The state of the
PLL_MODEx pins should be changed while RESET is held low.
The PLL loop filter should be connected to the PLL_LF pin. This
filter, shown in Figure 15, includes three passive components—
two capacitors and a resistor. The values of these components
do not need to be exact; the tolerance can be up to 10% for the
resistor and up to 20% for the capacitors. The 3.3 V signal shown in
Figure 15 can be connected to the AVDD supply of the chip.
ADAU1701
3.3V
475
PLL_LF
56nF
3.3nF
06
41
2-
0
15
Figure 15. PLL Loop Filter
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EVAL-ADAU1701MINIZ 制造商:Analog Devices 功能描述:ADAU1701MINIZ EvaluationBoard
EVAL-ADAU1702EB 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:SigmaDSP 28-56-Bit Audio Processor with Two ADCs and Four DACs
EVAL-ADAU1702EBZ 制造商:Analog Devices 功能描述:EVALBRD SIGMADSP28/56-B AUDIOPR2ADC/4DAC - Bulk
EVAL-ADAU1761Z 功能描述:BOARD EVAL FOR ADAU1761 RoHS:是 類(lèi)別:編程器，開(kāi)發(fā)系統(tǒng) >> 評(píng)估演示板和套件 系列:SigmaDSP® 標(biāo)準(zhǔn)包裝:1 系列:PSoC® 主要目的:電源管理，熱管理 嵌入式:- 已用 IC / 零件:- 主要屬性:- 次要屬性:- 已供物品:板，CD，電源
EVAL-ADAU1781Z 功能描述:BOARD EVAL FOR ADAU1781 RoHS:是 類(lèi)別:編程器，開(kāi)發(fā)系統(tǒng) >> 評(píng)估演示板和套件 系列:SigmaDSP® 標(biāo)準(zhǔn)包裝:1 系列:- 主要目的:電信，線(xiàn)路接口單元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要屬性:T1/J1/E1 LIU 次要屬性:- 已供物品:板，電源，線(xiàn)纜，CD 其它名稱(chēng):82EBV2081
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