- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄15529 > EVAL-ADAU1701MINIZ (Analog Devices Inc)BOARD EVAL SIGMADSP AUD ADAU1701 PDF資料下載
參數(shù)資料
| 型號： | EVAL-ADAU1701MINIZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 17/53頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL SIGMADSP AUD ADAU1701 |
| 標準包裝： | 1 |
| 系列： | SigmaDSP® |
| 類型： | DSP：音頻 |
| 適用于相關產(chǎn)品： | ADAU1701 |
| 所含物品： | 板，線纜 |
| 產(chǎn)品目錄頁面： | 776 (CN2011-ZH PDF) |
| 相關產(chǎn)品： | ADAU1701JSTZ-RL-ND - IC AUDIO PROC 2ADC/4DAC 48-LQFP ADAU1701JSTZ-ND - IC AUDIO PROC 2ADC/4DAC 48-LQFP |
| 其它名稱： | ADAU1701MINIBZ ADAU1701MINIBZ-ND ADAU1701MINIZ ADAU1701MINIZ-ND |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁當前第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁
ADAU1701
Rev. B | Page 23 of 52
I2C PORT
The ADAU1701 supports a 2-wire serial (I2C-compatible)
microprocessor bus driving multiple peripherals. Two pins,
serial data (SDA) and serial clock (SCL), carry information
between the ADAU1701 and the system I2C master controller.
In I2C mode, the ADAU1701 is always a slave on the bus,
meaning it cannot initiate a data transfer. Each slave device is
recognized by a unique address. The address byte format is
shown in Table 15. The ADAU1701 slave addresses are set with
the ADDR0 and ADDR1 pins. The address resides in the first
seven bits of the I2C write. The LSB of this byte sets either a read
or write operation. Logic Level 1 corresponds to a read operation,
and Logic Level 0 corresponds to a write operation. Bit 5 and
Bit 6 of the address are set by tying the ADDRx pins of the
ADAU1701 to Logic Level 0 or Logic Level 1. The full byte
addresses, including the pin settings and read/write (R/W) bit,
are shown in
.
Burst mode addressing, where the subaddresses are automati-
cally incremented at word boundaries, can be used for writing
large amounts of data to contiguous memory locations. This
increment happens automatically after a single-word write unless
a stop condition is encountered. The registers and RAMs in the
ADAU1701 range in width from one to five bytes, so the auto-
increment feature knows the mapping between subaddresses and
the word length of the destination register (or memory location).
A data transfer is always terminated by a stop condition.
Both SDA and SCL should have 2.2 kΩ pull-up resistors on the
lines connected to them. The voltage on these signal lines should
not be more than IOVDD (3.3 V).
Table 15. ADAU1701 I2C Address Byte Format
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
0
1
0
1
ADDR1
ADDR0
R/W
Table 16. ADAU1701 I2C Addresses
ADDR1
ADDR0
R/W
Slave Address
0
0x68
0
1
0x69
0
1
0
0x6A
0
1
0x6B
1
0
0x6C
1
0
1
0x6D
1
0
0x6E
1
0x6F
Addressing
Initially, each device on the I2C bus is in an idle state monitoring
the SDA and SCL lines for a start condition and the proper address.
The I2C master initiates a data transfer by establishing a start
condition, defined by a high-to-low transition on SDA while
SCL remains high. This indicates that an address/data stream
follows. All devices on the bus respond to the start condition
and shift the next eight bits (the 7-bit address plus the R/W bit)
MSB first. The device that recognizes the transmitted address
responds by pulling the data line low during the ninth clock
pulse. This ninth bit is known as an acknowledge bit. All other
devices withdraw from the bus at this point and return to the
idle condition. The R/W bit determines the direction of the
data. A Logic 0 on the LSB of the first byte means the master
writes information to the peripheral, whereas a Logic 1 means
the master reads information from the peripheral after writing
the subaddress and repeating the start address. A data transfer
takes place until a stop condition is encountered. A stop condi-
tion occurs when SDA transitions from low to high while SCL
is held high.
shows the timing of an I2C write, and
shows an I2C read.
Stop and start conditions can be detected at any stage during the
data transfer. If these conditions are asserted out of sequence with
normal read and write operations, the ADAU1701 immediately
jumps to the idle condition. During a given SCL high period,
the user should only issue one start condition, one stop condition,
or a single stop condition followed by a single start condition. If
an invalid subaddress is issued by the user, the ADAU1701 does
not issue an acknowledge and returns to the idle condition. If
the user exceeds the highest subaddress while in auto-increment
mode, one of two actions is taken. In read mode, the ADAU1701
outputs the highest subaddress register contents until the master
device issues a no acknowledge, indicating the end of a read. A
no-acknowledge condition is where the SDA line is not pulled
low on the ninth clock pulse on SCL. On the other hand, if the
highest subaddress location is reached while in write mode, the
data for the invalid byte is not loaded into any subaddress register,
a no acknowledge is issued by the ADAU1701, and the part returns
to the idle condition.
相關PDF資料 |
PDF描述 |
|---|---|
| RBA15DTMI | CONN EDGECARD 30POS R/A .125 SLD |
| V300C24C75BF2 | CONVERTER MOD DC/DC 24V 75W |
| BQ2057DGKRG4 | IC LI-ION LDO CHRG MGMT 8-MSOP |
| AIUR-06-821K | INDUCTOR POWER 820UH 10% T/H |
| RBA15DTBI | CONN EDGECARD 30POS R/A .125 SLD |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| EVAL-ADAU1701MINIZ | 制造商:Analog Devices 功能描述:ADAU1701MINIZ EvaluationBoard |
| EVAL-ADAU1702EB | 制造商:AD 制造商全稱:Analog Devices 功能描述:SigmaDSP 28-56-Bit Audio Processor with Two ADCs and Four DACs |
| EVAL-ADAU1702EBZ | 制造商:Analog Devices 功能描述:EVALBRD SIGMADSP28/56-B AUDIOPR2ADC/4DAC - Bulk |
| EVAL-ADAU1761Z | 功能描述:BOARD EVAL FOR ADAU1761 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:SigmaDSP® 標準包裝:1 系列:PSoC® 主要目的:電源管理，熱管理 嵌入式:- 已用 IC / 零件:- 主要屬性:- 次要屬性:- 已供物品:板，CD，電源 |
| EVAL-ADAU1781Z | 功能描述:BOARD EVAL FOR ADAU1781 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:SigmaDSP® 標準包裝:1 系列:- 主要目的:電信，線路接口單元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要屬性:T1/J1/E1 LIU 次要屬性:- 已供物品:板，電源，線纜，CD 其它名稱:82EBV2081 |
發(fā)布緊急采購，3分鐘左右您將得到回復。