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參數(shù)資料
| 型號： | EVAL-AD7760EDZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 11/37頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL CONTROL AD7760 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 2.5M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 輸入范圍： | ±3.25 Vpp |
| 在以下條件下的電源（標(biāo)準(zhǔn)）： | 958mW @ 2.5MSPS |
| 工作溫度： | -40°C ~ 85°C |
| 已用 IC / 零件： | AD7760 |
| 已供物品： | 板，CD |
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AD7760
Rev. A | Page 18 of 36
THEORY OF OPERATION
The AD7760 employs a Σ-Δ conversion technique to convert
the analog input into an equivalent digital word. The modulator
samples the input waveform and outputs an equivalent digital
word to the digital filter at a rate equal to ICLK.
By employing oversampling, the quantization noise is spread
across a wide bandwidth from 0 to fICLK. This means that the
noise energy contained in the signal band of interest is reduced
(see Figure 40a). To further reduce the quantization noise in the
signal band of interest, a high order modulator is employed to
shape the noise spectrum so that most of the noise energy is
shifted out of the signal band (see Figure 40b).
The digital filtering that follows the modulator removes the
large out-of-band quantization noise (see Figure 40c) while also
reducing the data rate from fICLK at the input of the filter to
fICLK/8 or less at the output of the filter, depending on the
decimation rate used.
Digital filtering has certain advantages over analog filtering: It
does not introduce significant noise or distortion and can be
made perfectly linear in terms of phase.
The AD7760 employs three FIR filters in series. By using
different combinations of decimation ratios, filter selection,
and bypassing, data can be obtained from the AD7760 at a large
range of data rates. Multibit data from the modulator can be
obtained at the ICLK rate (see Modulator Data Output Mode
section). The first filter receives the data from the modulator at
a maximum frequency of 20 MHz and decimates it by 4 to output
the data at 5 MHz. The partially filtered data can be output at
this stage. The second filter allows the decimation rate to be
chosen from 2× to 32× or to be completely bypassed.
The third filter has a fixed decimation rate of 2×, is user
programmable, and has a default configuration. It is described
in detail in the Programmable FIR Filter section. This filter can
also be bypassed.
Table 6 shows some characteristics of the default filter. The
group delay of the filter is defined to be the delay to the center
of the impulse response and is equal to the computation plus
the filter delays. The delay until valid data is available (the
DVALID status bit is set) is equal to twice the filter delay plus
the computation delay.
QUANTIZATION NOISE
fICLK\2
BAND OF INTEREST
a.
fICLK\2
NOISE SHAPING
BAND OF INTEREST
b.
fICLK\2
BAND OF INTEREST
DIGITAL FILTER CUTOFF FREQUENCY
c.
04
97
5-
03
7
Figure 40. Σ-Δ ADC
Table 6. Configuration with Default Filter
ICLK
Frequency
Filter 1
Filter 2
Filter 3
Data State
Computation
Delay
Filter Delay
Pass-Band
Bandwidth
Output Data
Rate (ODR)
20 MHz
Bypassed
Unfiltered
0
10 MHz
20 MHz
4×
Bypassed
Partially filtered
0.325 μs
1.2 μs
1.35 MHz
5 MHz
20 MHz
4×
Bypassed
2×
Fully filtered
1.075 μs
10.8 μs
1 MHz
2.5 MHz
20 MHz
4×
2×
Bypassed
Partially filtered
1.35 μs
3.6 μs
562.5 kHz
2.5 MHz
20 MHz
2×
Fully filtered
1.625 μs
22.8 μs
500 kHz
1.25 MHz
20 MHz
4×
Bypassed
Partially filtered
1.725 μs
6 μs
281.25 kHz
1.25 MHz
20 MHz
4×
2×
Fully filtered
1.775 μs
44.4 μs
250 kHz
625 kHz
20 MHz
4×
8x
Bypassed
Partially filtered
2.6 μs
10.8 μs
140.625 kHz
625 kHz
20 MHz
4×
8×
2×
Fully filtered
2.25 μs
87.6 μs
125 kHz
312.5 kHz
20 MHz
4×
16×
Bypassed
Partially filtered
4.175 μs
20.4 μs
70.3125 kHz
312.5 kHz
20 MHz
4×
16×
2×
Fully filtered
3.1 μs
174 μs
62.5 kHz
156.25 kHz
20 MHz
4×
32×
Bypassed
Partially filtered
7.325 μs
39.6 μs
35.156 kHz
156.25 kHz
20 MHz
4×
32×
2×
Fully filtered
4.65 μs
346.8 μs
31.25 kHz
78.125 kHz
12.288 MHz
4×
8×
2×
Fully filtered
3.66 μs
142.6 μs
76.8 kHz
192 kHz
12.288 MHz
4×
16×
2×
Fully filtered
5.05 μs
283.2 μs
38.4 kHz
96 kHz
12.288 MHz
4×
32×
Bypassed
Partially filtered
11.92 μs
64.45 μs
21.6 kHz
96 kHz
12.288 MHz
4×
32×
2×
Fully filtered
7.57 μs
564.5 μs
19.2 kHz
48 kHz
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EVAL-AD7762EB | 制造商:Analog Devices 功能描述:EVALUATION CONTROL BOARD I.C. - Bulk |
| EVAL-AD7762EBZ | 制造商:Analog Devices 功能描述:EVALUATION CONTROL BOARD I.C. - Bulk |
| EVAL-AD7762EDZ | 功能描述:BOARD EVAL CONTROL AD7762 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 模數(shù)轉(zhuǎn)換器 (ADC) 系列:- 產(chǎn)品培訓(xùn)模塊:Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- ADC 的數(shù)量:1 位數(shù):12 采樣率（每秒）:94.4k 數(shù)據(jù)接口:USB 輸入范圍:±VREF/2 在以下條件下的電源（標(biāo)準(zhǔn)）:- 工作溫度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，軟件 |
| EVAL-AD7763EB | 制造商:Analog Devices 功能描述:EVALUATION BOARD I.C. - Bulk |
| EVAL-AD7763EBZ | 制造商:Analog Devices 功能描述:EVALUATION BOARD I.C. - Bulk |
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