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AD7262
Rev. 0 | Page 26 of 32
CS
SCLK
15
19
DOUTA
THREE-STATE
t4
23
4
20
t5
THREE-
STATE
18
DB9A
DB10A
DB11A
21
22
29
30
31
DB1A
DB0A
DOUTB
THREE-STATE
THREE-
STATE
DB9B
DB10B
DB11B
DB1B
DB0B
t2
t8
FIRST DATA BIT CLOCKED OUT
ON THE 19TH FALLING EDGE
FIRST DATA BIT READ
ON 20TH RISING EDGE
07
60
6-
03
3
Figure 33. Serial Interface Timing Diagram When Reading Data on the 20th Rising SCLK Edge with a 40 MHz SCLK
CS
30
31
29
21
20
19
18
DOUTA
THREE-STATE
THREE-
STATE
SCLK
12
43
44
45
DB13A
DB12A
DB1A
DB0A
DB13B
DB12B
DB1B
DB0B
t10
07
60
6-
03
4
Figure 34. Reading Data from Both ADCs on One DOUT Line with 45 SCLKs
CS
SCLK
1
5
19
DOUTA
THREE-STATE
t4
2
34
20
t5
THREE-
STATE
t7
t3
18
DB9A
DB10A
DB11A
21
29
30
31
DB1A
DB0A
DOUTB
THREE-STATE
THREE-
STATE
DB9B
DB10B
DB11B
DB1B
DB0B
t2
t9
t8
tQUIET
t6
FIRST DATA BIT CLOCKED
OUT ON THIS EDGE
FIRST DATA BIT READ
ON THIS EDGE
0
76
06
-03
5
Figure 35. Serial Interface Timing Diagram When Reading Data on the Falling SCLK Edge with a Slow SCLK Frequency