參數(shù)資料
型號(hào)： EVAL-AD7262EDZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 10/33頁(yè)
文件大小： 0K
描述： BOARD EVAL CONTROL AD7262
標(biāo)準(zhǔn)包裝： 1
ADC 的數(shù)量： 2
位數(shù)： 12
采樣率（每秒）： 1M
數(shù)據(jù)接口： 串行
輸入范圍： 5 Vpp
在以下條件下的電源（標(biāo)準(zhǔn)）： 120mW @ 1MSPS
工作溫度： -40°C ~ 105°C
已用 IC / 零件： AD7262
已供物品： 板，CD
AD7262
Rev. 0 | Page 17 of 32
REFERENCE
The AD7262/AD7262-5 can operate with either the internal
2.5 V on-chip reference or an externally applied reference. The
logic state of the REFSEL pin determines whether the internal
reference is used. The internal reference is selected for both ADCs
when the REFSEL pin is tied to logic high. If the REFSEL pin is
tied to AGND, an external reference can be supplied through
the VREFA and/or VREFB pins. On power-up, the REFSEL pin
must be tied to either a low or high logic state for the part to
operate. Suitable reference sources for the AD7262/AD7262-5
The internal reference circuitry consists of a 2.5 V band gap
reference and a reference buffer. When the AD7262/AD7262-5
are operated in internal reference mode, the 2.5 V internal
reference is available at the VREFA and VREFB pins, which should
be decoupled to AGND using a 1 μF capacitor. It is recommended
that the internal reference be buffered before applying it elsewhere
in the system. The internal reference is capable of sourcing up
to 90 μA of current when the converter is static. If the internal
reference operation is required for the ADC conversion, the
REFSEL pin must be tied to logic high on power-up. The refer-
ence buffer requires 240 μs to power up and charge the 1 μF
decoupling capacitor during the power-up time.
TYPICAL CONNECTION DIAGRAMS
Figure 26 and Figure 27 are typical connection diagrams for the
AD7262/AD7262-5. In these configurations, the AGND pin is
connected to the analog ground plane of the system, and the
DGND pin is connected to the digital ground plane of the system.
The analog inputs on the AD7262/AD7262-5 are true differen-
tial and have an input impedance in excess of 1 GΩ; thus, no
driving op amps are required. The AD7262/AD7262-5 can operate
with either an internal or an external reference. In Figure 26, the
AD7262/AD7262-5 are configured to operate in control register
mode; thus, G0 to G3, PD1, and PD2 can be connected to ground
(low logic state). Figure 27 has the gain pins configured for a gain
of 2 setup; thus, the device is in pin-driven mode. Both circuit
configurations illustrate the use of the internal 2.5 V reference
The CA_CBVCC and the CC_CDVCC pins can be connected to either
a 3 V or a 5 V supply voltage. The AVCC pin must be connected
to a 5 V supply. All supplies should be decoupled with a 100 nF
capacitor at the device pin, and some supply sources may require a
10 μF capacitor where the source is supplied to the circuit board.
The VDRIVE pin is connected to the supply voltage of the micro-
processor. The voltage applied to the VDRIVE input controls the
voltage of the serial interface. VDRIVE can be set to 3 V or 5 V.
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