參數(shù)資料
型號(hào)： EVAL-AD5757SDZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 33/44頁(yè)
文件大小： 0K
描述： BOARD EVAL FOR AD5757
標(biāo)準(zhǔn)包裝： 1
DAC 的數(shù)量： 4
位數(shù)： 16
數(shù)據(jù)接口： 串行
設(shè)置時(shí)間： 15µs
DAC 型： 電流
工作溫度： -40°C ~ 105°C
已供物品： 板
已用 IC / 零件： AD5757
Data Sheet
AD5757
Rev. D | Page 39 of 44
0
4
12
8
16
24
20
28
32
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
AI
CC
CURRE
NT
(A)
0mA TO 24mA RANGE
1k LOAD
fSW = 410kHz
INDUCTOR = 10H (XAL4040-103)
TA = 25°C
0
0.5
1.0
1.5
2.0
2.5
I OU
T
_x
CURRE
NT
(m
A
)/
V
BO
O
S
T_
xVO
LT
A
G
E
(V)
TIME (ms)
AICC
IOUT
VBOOST
092
25
-18
5
Figure 59. AICC Current vs. Time for 24 mA Step Through 1 kΩ Load
with External 51 kΩ Compensation Resistor
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
AI
CC
CURRE
NT
(
A)
0mA TO 24mA RANGE
500 LOAD
fSW = 410kHz
INDUCTOR = 10H (XAL4040-103)
TA = 25°C
0
4
12
8
16
24
20
28
32
0
0.5
1.0
1.5
2.0
2.5
I OU
T
_x
CU
RRE
NT
(m
A
)/
V
B
OOS
T
_x
V
O
LTA
G
E
(
V
)
TIME (ms)
AICC
IOUT
VBOOST
092
25-
186
Figure 60. AICC Current vs. Time for 24 mA Step Through 500 Ω Load
with External 51 kΩ Compensation Resistor
Using slew rate control can greatly reduce the AVCC supplies cur-
rent requirements, as shown in Figure 61. When using slew rate
control, attention should be paid to the fact that the output cannot
slew faster than the dc-to-dc converter. The dc-to-dc converter
slews slowest at higher currents through large (for example, 1 kΩ)
loads. This slew rate is also dependent on the configuration of
the dc-to-dc converter. Two examples of the dc-to-dc converter’s
output slew are shown in Figure 59 and Figure 60 (VBOOST corre-
sponds to the dc-to-dc converter’s output voltage).
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
AI
CC
CURRE
NT
(A)
0mA TO 24mA RANGE
1k LOAD
fSW = 410kHz
INDUCTOR = 10H (XAL4040-103)
TA = 25°C
0
4
12
8
16
24
20
28
32
0
1
2
345
6
I OU
T
_x
CURRE
NT
(m
A
)/
V
BO
O
S
T_
xVO
LT
A
G
E
(V)
TIME (ms)
AICC
IOUT
VBOOST
092
25
-18
7
Figure 61. AICC Current vs. Time for 24 mA Step Through 1 kΩ Load
with Slew Rate Control
EXTERNAL PMOS MODE
The AD5757 can also be used with an external PMOS transistor
per channel, as shown in Figure 62. This mode can be used to
limit the on-chip power dissipation of the AD5757, though this
will not reduce the power dissipation of the total system. The
IGATE functionality is not typically required when using the
dynamic power control feature so Figure 62 shows the configura-
tion of the device for a fixed VBOOST_x supply.
In this configuration the SWx pin are left floating and the
GNDSWx pin is grounded. The VBOOST_x pin is connected to a
minimum supply of 7.5 V and a maximum supply of 33 V. This
supply can be sized according to the maximum load required to
be driven.
The IGATE functionality works by holding the gate of the
external PMOS transistor at (VBOOST_x 5 V). This means that
the majority of the channels power dissipation will take place in
this external PMOS transistor.
The external PMOS transistor should be chosen tolerate a VDS
voltage of at least VBOOST_x, as well as to handle the power
dissipation required. This external PMOS transistor typically
has minimal effect on the current output performance.
0
9225-
190
R1
R2
R3
RSET_A
RLOAD
SWGNDA
VBOOST_A
(VBOOST_A –5V)
SWA
CHARTA
IGATEA
CURRENT OUTPUT
DAC CHANNEL A
(LEFT FLOATING)
IOUT_A
DAC A
5.0V
AVCC
Figure 62. Configuration off a Particular Channel Using IGATE
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