參數(shù)資料
型號(hào)： EVAL-AD5757SDZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 28/44頁(yè)
文件大?。?/td> 0K
描述： BOARD EVAL FOR AD5757
標(biāo)準(zhǔn)包裝： 1
DAC 的數(shù)量： 4
位數(shù)： 16
數(shù)據(jù)接口： 串行
設(shè)置時(shí)間： 15µs
DAC 型： 電流
工作溫度： -40°C ~ 105°C
已供物品： 板
已用 IC / 零件： AD5757
AD5757
Data Sheet
Rev. D | Page 34 of 44
DEVICE FEATURES
OUTPUT FAULT
The AD5757 is equipped with a FAULT pin, an active low open-
drain output allowing several AD5757 devices to be connected
together to one pull-up resistor for global fault detection. The
FAULT pin is forced active by any one of the following fault
scenarios:
The voltage at IOUT_x attempts to rise above the compliance
range, due to an open-loop circuit or insufficient power
supply voltage. The internal circuitry that develops the
fault output avoids using a comparator with windowed
limits because this requires an actual output error before
the FAULT output becomes active. Instead, the signal is
generated when the internal amplifier in the output stage
has less than approximately 1 V of remaining drive
capability. Thus, the FAULT output activates slightly before
the compliance limit is reached.
An interface error is detected due to a PEC failure. See the
If the core temperature of the AD5757 exceeds
approximately 150°C.
The IOUT_x fault, PEC error, and over TEMP bits of the status
register are used in conjunction with the FAULT output to
inform the user which one of the fault conditions caused the
FAULT output to be activated.
DIGITAL OFFSET AND GAIN CONTROL
Each DAC channel has a gain (M) and offset (C) register, which
allow trimming out of the gain and offset errors of the entire
signal chain. Data from the DAC data register is operated on by
a digital multiplier and adder controlled by the contents of the
M and C registers. The calibrated DAC data is then stored in the
DAC input register.
DAC
REGISTER
DAC
INPUT
REGISTER
M
REGISTER
C
REGISTER
09225-
075
Figure 53. Digital Offset and Gain control
Although Figure 53 indicates a multiplier and adder for each
channel, there is only one multiplier and one adder in the device,
and they are shared among all four channels. This has
implications for the update speed when several channels are
updated at once (see Table 3).
Each time data is written to the M or C register, the output is
not automatically updated. Instead, the next write to the DAC
channel uses these M and C values to perform a new calibration
and automatically updates the channel.
The output data from the calibration is routed to the DAC input
register. This is then loaded to the DAC as described in the
Theory of Operation section. Both the gain register and the
offset register have 16 bits of resolution. The correct method to
calibrate the gain/offset is to first calibrate out the gain and then
calibrate the offset.
The value (in decimal) that is written to the DAC input register
can be calculated by
15
16
2
)
1
(
+
×
=
C
M
D
Code
r
DACRegiste
(1)
where:
D is the code loaded to the DAC channel’s input register.
M is the code in the gain register (default code = 216 – 1).
C is the code in the offset register (default code = 215).
STATUS READBACK DURING A WRITE
The AD5757 has the ability to read back the status register
contents during every write sequence. This feature is enabled
via the STATREAD bit in the main control register. This allows
the user to continuously monitor the status register and act
quickly in the case of a fault.
When status readback during a write is enabled, the contents of
the 16-bit status register (see Table 29) are output on the SDO
pin, as shown in Figure 5.
The AD5757 powers up with this feature disabled. When this is
enabled, the normal readback feature is not available, except for
the status register. To read back any other register, clear the
STATREAD bit first before following the readback sequence.
STATREAD can be set high again after the register read.
ASYNCHRONOUS CLEAR
CLEAR is an active high, edge-sensitive input that allows the
output to be cleared to a preprogrammed 16-bit code. This code
is user programmable via a per channel 16-bit clear code register.
For a channel to clear, that channel must be enabled to be
cleared via the CLR_EN bit in the channel’s DAC control
register. If the channel is not enabled to be cleared, the output
remains in its current state independent of the CLEAR pin level.
When the CLEAR signal is returned low, the relevant outputs
remain cleared until a new value is programmed.
PACKET ERROR CHECKING
To verify that data has been received correctly in noisy environ-
ments, the AD5757 offers the option of packet error checking
based on an 8-bit cyclic redundancy check (CRC-8). The device
controlling the AD5757 should generate an 8-bit frame check
sequence using the polynomial
C(x) = x8 + x2 + x1 + 1
This is added to the end of the data-word, and 32 bits are sent
to the AD5757 before taking SYNC high. If the AD5757 sees a
32-bit frame, it performs the error check when SYNC goes high.
If the check is valid, the data is written to the selected register.
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