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參數(shù)資料
| 型號(hào)： | EPF10K100EQI208-2 |
| 英文描述： | Field Programmable Gate Array (FPGA) |
| 中文描述： | 現(xiàn)場(chǎng)可編程門陣列（FPGA） |
| 文件頁(yè)數(shù)： | 9/120頁(yè) |
| 文件大?。?/td> | 1901K |
| 代理商： | EPF10K100EQI208-2 |
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106
Altera Corporation
FLEX 10KE Embedded Programmable Logic Family Data Sheet
Notes to tables:
(1)
All pins that are not listed are user I/O pins.
(2)
EPF10K50E, EPF10K100E, and EPF10K100B devices are pin-compatible with the EPF10K130E devices in the same
package if pins 20, 76, and 159 are connected to VCCINT. The MAX+PLUS II software performs this function
automatically when future migration is set.
(3)
EPF10K50E, EPF10K100E, and EPF10K100B devices are pin-compatible with the EPF10K200E devices in the same
package if pins 20, 40, 76, 139, 159, 187, and 225 are connected to VCCINT. The MAX+PLUS II software performs this
function automatically when future migration is set.
(4)
This pin is a dedicated pin; it is not available as a user I/O pin.
(5)
This pin can be used as a user I/O pin if it is not used for its device-wide or configuration function.
(6)
This pin can be used as a user I/O pin after configuration.
(7)
This pin is tri-stated in user mode.
(8)
The optional JTAG pin TRST is not used in the 144-pin TQFP package.
(9)
This pin drives the ClockLock and ClockBoost circuitry.
(10) This pin shows the status of the ClockLock and ClockBoost circuitry. When the ClockLock and ClockBoost circuitry
is locked to the incoming clock and generates an internal clock, LOCK is driven high. LOCK remains high if a periodic
clock stops clocking. The LOCK function is optional; if the LOCK output is not used, this pin is a user I/O pin.
(11) This pin is the power or ground for the ClockLock and ClockBoost circuitry. To ensure noise resistance, the power
and ground supply to the ClockLock and ClockBoost circuitry should be isolated from the power and ground to the
rest of the device. If the ClockLock or ClockBoost circuitry is not used, this power or ground pin should be
connected to VCCINT or GNDINT, respectively.
(12) When using the EPF10K100B device, connect this pin to VCCINT.
(13) When using the EPF10K100B device, connect this pin to GNDINT.
(14) The user I/O pin count includes dedicated input pins, dedicated clock pins, and all I/O pins.
in 256-pin FineLine BGA, 484-pin FineLine BGA, and 672-pin FineLine
BGA packages.
Table 87. FLEX 10KE FineLine BGA Device Pin-Outs (Part 1 of 4)
Pin Name
256-Pin
FineLine BGA
EPF10K30E
256-Pin
FineLine BGA
EPF10K50E
EPF10K50S
EPF10K100E
EPF10K100B
484-Pin
FineLine BGA
EPF10K30E
MSEL0
P1
U4
MSEL1
R1
V4
nSTATUS
T16
W19
nCONFIG
N4
T7
DCLK
B2
E5
CONF_DONE
C15
F18
INIT_DONE
G16
K19
nCE
B1
E4
nCEO
B16
E19
nWS
B14
E17
nRS
C14
F17
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| EPF10K100EQI208-2DX | ASIC |
| EPF10K100EQI208-3DX | ASIC |
| EPF10K130EBC600-1X | Field Programmable Gate Array (FPGA) |
| EPF10K130EBC600-2 | Field Programmable Gate Array (FPGA) |
| EPF10K130EBC600-2X | Field Programmable Gate Array (FPGA) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EPF10K100EQI208-2DX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC |
| EPF10K100EQI208-3DX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC |
| EPF10K100EQI240-1DX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC |
| EPF10K100EQI240-2DX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC |
| EPF10K100EQI240-3DX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC |
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