參數(shù)資料
型號(hào)： EPF10K100EQI208-2
英文描述： Field Programmable Gate Array (FPGA)
中文描述： 現(xiàn)場(chǎng)可編程門陣列（FPGA）
文件頁數(shù)： 115/120頁
文件大?。?/td> 1901K
代理商： EPF10K100EQI208-2
94
Altera Corporation
FLEX 10KE Embedded Programmable Logic Family Data Sheet
Notes to tables:
(1)
All timing parameters are described in Tables 24 through 30 in this data sheet.
(2)
All EPF10K200S timing values are preliminary.
(3)
These parameters are specified by characterization.
(4)
This parameter is measured without the use of the ClockLock or ClockBoost circuits.
(5)
This parameter is measured with the use of the ClockLock or ClockBoost circuits.
Power
Consumption
The supply power (P) for FLEX 10KE devices can be calculated with the
following equation:
P = PINT + PIO = (ICCSTANDBY + ICCACTIVE) × VCC + PIO
The ICCACTIVE value depends on the switching frequency and the
application logic. This value is calculated based on the amount of current
that each LE typically consumes. The PIO value, which depends on the
device output load characteristics and switching frequency, can be
calculated using the guidelines given in Application Note 74 (Evaluating
1
Compared to the rest of the device, the embedded array
consumes a negligible amount of power. Therefore, the
embedded array can be ignored when calculating supply
current.
Table 81. EPF10K200S External Bidirectional Timing Parameters
Symbol
Speed Grade
Unit
-1
-2
-3
Min
Max
Min
Max
Min
Max
tINSUBIDIR (4)
2.3
3.4
4.4
ns
tINHBIDIR (4)
0.0
ns
tOUTCOBIDIR (4)
2.0
3.7
2.0
4.4
2.0
6.3
ns
tXZBIDIR (4)
6.9
7.6
9.2
ns
tZXBIDIR (4)
6.9
7.6
9.2
ns
tINSUBIDIR (5)
3.3
4.4
–
tINHBIDIR (5)
0.0
–
tOUTCOBIDIR (5)
0.5
2.7
0.5
3.4
––
ns
tXZBIDIR (5)
5.9
6.6
–
ns
tZXBIDIR (5)
5.9
6.6
–
ns
相關(guān)PDF資料
PDF描述
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EPF10K100EQI208-2DX 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC
EPF10K100EQI208-3DX 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC
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EPF10K100EQI240-2DX 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC
EPF10K100EQI240-3DX 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC
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