參數(shù)資料
型號： EP20K60EFC324
廠商： ALTERA CORP
元件分類： PLD
英文描述： LOADABLE PLD, PBGA324
封裝： 19 X 19 MM, 1 MM PITCH, FINE LINE, BGA-324
文件頁數(shù)： 32/114頁
文件大?。?/td> 4116K
代理商： EP20K60EFC324
IGLOO nano DC and Switching Characteristics
2- 10
Advance v0.2
Power Consumption of Various Internal Resources
Table 2-14 Different Components Contributing to Dynamic Power Consumption in IGLOO nano Devices
For IGLOO nano V2 or V5 Devices, 1.5 V Core Supply Voltage
Parameter
Definition
Device Specific Dynamic Power (W/MHz)
AGLN250 AGLN125 AGLN060 AGLN020 AGLN015 AGLN010
PAC1
Clock contribution of a Global Rib
11.03
9.3
PAC2
Clock contribution of a Global
Spine
1.58
0.81
0.41
PAC3
Clock contribution of a VersaTile
row
0.81
PAC4
Clock contribution of a VersaTile
used as a sequential module
0.11
PAC5
First contribution of a VersaTile
used as a sequential module
0.057
PAC6
Second contribution of a VersaTile
used as a sequential module
0.207
PAC7
Contribution of a VersaTile used as
a combinatorial module
0.17
PAC8
Average contribution of a routing
net
0.7
PAC9
Contribution of an I/O input pin
(standard-dependent)
PAC10
Contribution of an I/O output pin
(standard-dependent)
PAC11
Average contribution of a RAM
block during a read operation
25.00
N/A
PAC12
Average contribution of a RAM
block during a write operation
30.00
N/A
PAC13
Dynamic contribution for PLL
2.70
N/A
Table 2-15 Different Components Contributing to the Static Power Consumption in IGLOO nano Devices
For IGLOO nano V2 or V5 Devices, 1.5 V Core Supply Voltage
Parameter
Definition
Device -Specific Static Power (mW)
AGLN250 AGLN125 AGLN060 AGLN020 AGLN015 AGLN010
PDC1
Array static power in Active mode
PDC2
Array static power in Static (Idle)
mode
PDC3
Array static power in Flash*Freeze
mode
PDC4
2
Static PLL contribution
1.84
N/A
PDC5
Bank quiescent power
(VCCI-dependent)
Notes:
1. For a different output load, drive strength, or slew rate, Actel recommends using the Actel power
spreadsheet calculator or the SmartPower tool in Actel Libero Integrated Design Environment (IDE).
2. Minimum contribution of the PLL when running at lowest frequency.
相關(guān)PDF資料
PDF描述
EP20K60EFC484-1 LOADABLE PLD, PBGA484
EP20K60EFC484-2 LOADABLE PLD, PBGA484
EP20K60EFC484-3 LOADABLE PLD, PBGA484
EP20K60EFC484 LOADABLE PLD, PBGA484
EP20K60EFC672-1 LOADABLE PLD, PBGA672
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EP20K60EFC324-1 功能描述:FPGA - 現(xiàn)場可編程門陣列 CPLD - APEX 20K 256 Macro 196 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP20K60EFC324-1ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA
EP20K60EFC324-1N 功能描述:FPGA - 現(xiàn)場可編程門陣列 CPLD - APEX 20K 256 Macro 196 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP20K60EFC324-1X 功能描述:FPGA - 現(xiàn)場可編程門陣列 CPLD - APEX 20K 256 Macro 196 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP20K60EFC324-2 功能描述:FPGA - 現(xiàn)場可編程門陣列 CPLD - APEX 20K 256 Macro 196 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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