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參數(shù)資料
| 型號： | EBD21RD4ADNA-6B-E |
| 廠商： | ELPIDA MEMORY INC |
| 元件分類： | DRAM |
| 英文描述： | 2GB Registered DDR SDRAM DIMM (256M words X72 bits, 2 Ranks) |
| 中文描述： | 256M X 72 DDR DRAM MODULE, 0.7 ns, DMA184 |
| 封裝： | LEAD FREE, DIMM-184 |
| 文件頁數(shù)： | 12/19頁 |
| 文件大?。?/td> | 201K |
| 代理商： | EBD21RD4ADNA-6B-E |
EBD21RD4ADNA-E
Data Sheet E0606E10 (Ver. 1.0)
12
DC Characteristics 2 (TA = 0 to +70°C, VDD, VDDQ = 2.5V ± 0.2V, VSS = 0V)
(DDR SDRAM Component Specification)
Parameter
Symbol
min.
max.
Unit
Test condition
Note
Input leakage current
ILI
–2
2
μA
VDD
≥
VIN
≥
VSS
Output leakage current
ILO
–5
5
μA
VDDQ
≥
VOUT
≥
VSS
Output high current
IOH
–15.2
—
mA
VOUT = 1.95V
Output low current
IOL
15.2
—
mA
VOUT = 0.35V
Pin Capacitance (TA = 25°C, VDD, VDDQ = 2.5V ± 0.2V)
Parameter
Symbol
Pins
max.
Unit
Notes
Input capacitance
CI1
Address, /RAS, /CAS, /WE,
/CS, CKE
20
pF
1, 3
Input capacitance
CI2
CK, /CK
20
pF
1, 3
Data and DQS input/output
capacitance
Notes: 1. These parameters are measured on conditions: f = 100MHz, VOUT = VDDQ/2,
VOUT = 0.2V.
2. Dout circuits are disabled.
3. This parameter is sampled and not 100% tested.
CO
DQ, DQS, CB, DM
20
pF
1, 2, 3
AC Characteristics (TA = 0 to +70
°
C, VDD, VDDQ = 2.5V ± 0.2V, VSS = 0V)
(DDR SDRAM Component Specification)
-6B
-7A
-7B
Parameter
Clock cycle time
(CL = 2)
Symbol
min.
max.
min.
max
min.
max.
Unit Notes
tCK
7.5
12
7.5
12
10
12
ns
10
(CL = 2.5)
tCK
6
12
7.5
12
7.5
12
ns
CK high-level width
tCH
0.45
0.55
0.45
0.55
0.45
0.55
tCK
CK low-level width
tCL
0.45
0.55
0.45
0.55
0.45
0.55
tCK
CK half period
tHP
min
(tCH, tCL)
—
min
(tCH, tCL)
—
min
(tCH, tCL)
—
tCK
DQ output access time from CK, /CK tAC
–0.7
0.7
–0.75
0.75
–0.75
0.75
ns
2, 11
DQS output access time from CK,
/CK
tDQSCK –0.6
0.6
–0.75
0.75
–0.75
0.75
ns
2, 11
DQS to DQ skew
tDQSQ
—
0.45
—
0.5
—
0.5
ns
3
DQ/DQS output hold time from DQS tQH
tHP – tQHS —
tHP – tQHS —
tHP – tQHS —
ns
Data hold skew factor
tQHS
—
0.55
—
0.75
—
0.75
ns
Data-out high-impedance time from
CK, /CK
Data-out low-impedance time from
CK, /CK
tHZ
–0.7
0.7
–0.75
0.75
–0.75
0.75
ns
5, 11
tLZ
–0.7
0.7
–0.75
0.75
–0.75
0.75
ns
6, 11
Read preamble
tRPRE
0.9
1.1
0.9
1.1
0.9
1.1
tCK
Read postamble
tRPST
0.4
0.6
0.4
0.6
0.4
0.6
tCK
DQ and DM input setup time
tDS
0.45
—
0.5
—
0.5
—
ns
8
DQ and DM input hold time
tDH
0.45
—
0.5
—
0.5
—
ns
8
DQ and DM input pulse width
tDIPW
1.75
—
1.75
—
1.75
—
ns
7
Write preamble setup time
tWPRES 0
—
0
—
0
—
ns
Write preamble
tWPRE
0.25
—
0.25
—
0.25
—
tCK
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| EBD21RD4ADNA-7A | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:2GB Registered DDR SDRAM DIMM (256M words X72 bits, 2 Ranks) |
| EBD21RD4ADNA-7A-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:2GB Registered DDR SDRAM DIMM (256M words X72 bits, 2 Ranks) |
| EBD21RD4ADNA-7B | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:2GB Registered DDR SDRAM DIMM (256M words X72 bits, 2 Ranks) |
| EBD21RD4ADNA-7B-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:2GB Registered DDR SDRAM DIMM (256M words X72 bits, 2 Ranks) |
| EBD21RD4ADNA-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:2GB Registered DDR SDRAM DIMM (256M words X72 bits, 2 Ranks) |
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