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參數(shù)資料
| 型號(hào)： | EBD21RD4ADNA-6B-E |
| 廠商： | ELPIDA MEMORY INC |
| 元件分類： | DRAM |
| 英文描述： | 2GB Registered DDR SDRAM DIMM (256M words X72 bits, 2 Ranks) |
| 中文描述： | 256M X 72 DDR DRAM MODULE, 0.7 ns, DMA184 |
| 封裝： | LEAD FREE, DIMM-184 |
| 文件頁(yè)數(shù)： | 11/19頁(yè) |
| 文件大?。?/td> | 201K |
| 代理商： | EBD21RD4ADNA-6B-E |
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EBD21RD4ADNA-E
Data Sheet E0606E10 (Ver. 1.0)
11
DC Characteristics 1 (TA = 0 to +70°C, VDD, VDDQ = 2.5V ± 0.2V, VSS = 0V)
Parameter
Symbol
Grade
max.
Unit
Test condition
Notes
Operating current (ACTV-PRE)
IDD0
-6B
-7A, -7B
-6B
-7A, -7B
-6B
-7A, -7B
-6B
-7A, -7B
-6B
-7A, -7B
-6B
-7A, -7B
-6B
-7A, -7B
-6B
-7A, -7B
-6B
-7A, -7B
-6B
-7A, -7B
-6B
-7A, -7B
-6B
-7A, -7B
4160
3700
4880
4330
395
385
1370
1180
1010
1000
1010
1000
2630
2260
5600
4870
5600
4870
7220
6670
430
420
10280
8650
mA
CKE
≥
VIH,
tRC = tRC (min.)
CKE
≥
VIH, BL = 4,
CL = 3.5, tRC = tRC (min.)
1, 2, 9
Operating current
(ACTV-READ-PRE)
IDD1
mA
1, 2, 5
Idle power down standby current IDD2P
mA
CKE
≤
VIL
4
Floating idle
Standby current
Quiet idle
Standby current
Active power down standby
current
IDD2F
mA
CKE
≥
VIH, /CS
≥
VIH
DQ, DQS, DM = VREF
CKE
≥
VIH, /CS
≥
VIH
DQ, DQS, DM = VREF
4, 5
IDD2Q
mA
4, 10
IDD3P
mA
CKE
≤
VIL
3
Active standby current
IDD3N
mA
CKE
≥
VIH, /CS
≥
VIH
tRAS = tRAS (max.)
CKE
≥
VIH, BL = 2,
CL = 3.5
CKE
≥
VIH, BL = 2,
CL = 3.5
tRFC = tRFC (min.),
Input
≤
VIL or
≥
VIH
Input
≥
VDD – 0.2 V
Input
≤
0.2 V
3, 5, 6
Operating current
(Burst read operation)
Operating current
(Burst write operation)
IDD4R
mA
1, 2, 5, 6
IDD4W
mA
1, 2, 5, 6
Auto refresh current
IDD5
mA
Self refresh current
IDD6
mA
Operating current
(4 banks interleaving)
Notes. 1. These IDD data are measured under condition that DQ pins are not connected.
2. One bank operation.
3. One bank active.
4. All banks idle.
5. Command/Address transition once per one cycle.
6. DQ, DM, DQS transition twice per one cycle.
7. 4 banks active. Only one bank is running at tRC = tRC (min.)
8. The IDD data on this table are measured with regard to tCK = tCK (min.) in general.
9. Command/Address transition once per one every two clock cycles.
10. Command/Address stable at
≥
VIH or
≤
VIL.
IDD7A
mA
BL = 4
1, 5, 6, 7
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EBD21RD4ADNA-7A | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:2GB Registered DDR SDRAM DIMM (256M words X72 bits, 2 Ranks) |
| EBD21RD4ADNA-7A-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:2GB Registered DDR SDRAM DIMM (256M words X72 bits, 2 Ranks) |
| EBD21RD4ADNA-7B | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:2GB Registered DDR SDRAM DIMM (256M words X72 bits, 2 Ranks) |
| EBD21RD4ADNA-7B-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:2GB Registered DDR SDRAM DIMM (256M words X72 bits, 2 Ranks) |
| EBD21RD4ADNA-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:2GB Registered DDR SDRAM DIMM (256M words X72 bits, 2 Ranks) |
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