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參數(shù)資料
| 型號： | EBD10RD4ADFA-7A |
| 廠商： | ELPIDA MEMORY INC |
| 元件分類： | DRAM |
| 英文描述： | RES MFLM 2K 0.1W 5% SMT0805 |
| 中文描述： | 128M X 72 DDR DRAM MODULE, 0.75 ns, DMA184 |
| 封裝： | DIMM-184 |
| 文件頁數(shù)： | 13/19頁 |
| 文件大?。?/td> | 219K |
| 代理商： | EBD10RD4ADFA-7A |
EBD10RD4ADFA
Data Sheet E0430E20 (Ver. 2.0)
13
-6B
-7A
-7B
Parameter
Symbol min.
max
min.
max
min.
max
Unit Notes
Address and control input hold
time
Address and control input pulse
width
Mode register set command cycle
time
Active to Precharge command
period
Active to Active/Auto refresh
command period
Auto refresh to Active/Auto refresh
command period
tIH
0.75
—
0.9
—
0.9
—
ns
8
tIPW
2.2
—
2.2
—
2.2
—
ns
7
tMRD
2
—
2
—
2
—
tCK
tRAS
42
120000
45
120000
45
120000
ns
tRC
60
—
65
—
65
—
ns
tRFC
72
—
75
—
75
—
ns
Active to Read/Write delay
tRCD
18
—
20
—
20
—
ns
Precharge to active command
period
Active to auto precharge delay
tRP
18
—
20
—
20
—
ns
tRAP
tRCD min.
—
tRCD min.
—
tRCD min.
—
ns
Active to active command period
tRRD
12
—
15
—
15
—
ns
Write recovery time
tWR
15
—
15
—
15
—
ns
Auto precharge write recovery and
precharge time
Internal write to Read command
delay
tDAL
(tWR/tCK)+
(tRP/tCK)
—
(tWR/tCK)+
(tRP/tCK)
—
(tWR/tCK)+
(tRP/tCK)
—
tCK 13
tWTR
1
—
1
—
1
—
tCK
Average periodic refresh interval
tREF
—
7.8
—
7.8
—
7.8
μs
Notes: 1. All the AC parameters listed in this data sheet is component specifications. For AC testing conditions,
refer to the corresponding component data sheet.
2. This parameter defines the signal transition delay from the cross point of CK and /CK. The signal
transition is defined to occur when the signal level crossing VTT.
3. The timing reference level is VTT.
4. Output valid window is defined to be the period between two successive transition of data out or DQS
(read) signals. The signal transition is defined to occur when the signal level crossing VTT.
5. tHZ is defined as DOUT transition delay from Low-Z to High-Z at the end of read burst operation. The
timing reference is cross point of CK and /CK. This parameter is not referred to a specific DOUT voltage
level, but specify when the device output stops driving.
6. tLZ is defined as DOUT transition delay from High-Z to Low-Z at the beginning of read operation. This
parameter is not referred to a specific DOUT voltage level, but specify when the device output begins
driving.
7. Input valid windows is defined to be the period between two successive transition of data input or DQS
(write) signals. The signal transition is defined to occur when the signal level crossing VREF.
8. The timing reference level is VREF.
9. The transition from Low-Z to High-Z is defined to occur when the device output stops driving. A specific
reference voltage to judge this transition is not given.
10. tCK (max.) is determined by the lock range of the DLL. Beyond this lock range, the DLL operation is not
assured.
11. tCK = tCK (min.) when these parameters are measured. Otherwise, absolute minimum values of these
values are 10% of tCK.
12. VDD is assumed to be 2.5V ± 0.2V. VDD power supply variation per cycle expected to be less than
0.4V/400 cycle.
13. tDAL = (tWR/tCK)+(tRP/tCK)
For each of the terms above, if not already an integer, round to the next highest integer.
Example: For –7A Speed at CL = 2.5, tCK = 7.5ns, tWR = 15ns and tRP= 20ns,
tDAL = (15ns/7.5ns) + (20ns/7.5ns) = (2) + (3)
tDAL = 5 clocks
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PDF描述 |
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| EBD10RD4ADFA | 1GB Registered DDR SDRAM DIMM (128M words x72 bits, 1 Rank) |
| EBD10RD4ADFA-6B | 1GB Registered DDR SDRAM DIMM (128M words x72 bits, 1 Rank) |
| EBD10RD4ADFA-7B | 1GB Registered DDR SDRAM DIMM (128M words x72 bits, 1 Rank) |
| EBD10RD4ADFA-7B-E | 1GB Registered DDR SDRAM DIMM (128M words x72 bits, 1 Rank) |
| EBD10RD4ADFA-E | 1GB Registered DDR SDRAM DIMM (128M words x72 bits, 1 Rank) |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| EBD10RD4ADFA-7A-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:1GB Registered DDR SDRAM DIMM (128M words x72 bits, 1 Rank) |
| EBD10RD4ADFA-7B | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:1GB Registered DDR SDRAM DIMM (128M words x72 bits, 1 Rank) |
| EBD10RD4ADFA-7B-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:1GB Registered DDR SDRAM DIMM (128M words x72 bits, 1 Rank) |
| EBD10RD4ADFA-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:1GB Registered DDR SDRAM DIMM (128M words x72 bits, 1 Rank) |
| EBD11ED8ABFA | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:1GB Unbuffered DDR SDRAM DIMM |
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