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參數(shù)資料
| 型號(hào)： | EBD10RD4ADFA-7A |
| 廠商： | ELPIDA MEMORY INC |
| 元件分類： | DRAM |
| 英文描述： | RES MFLM 2K 0.1W 5% SMT0805 |
| 中文描述： | 128M X 72 DDR DRAM MODULE, 0.75 ns, DMA184 |
| 封裝： | DIMM-184 |
| 文件頁(yè)數(shù)： | 12/19頁(yè) |
| 文件大?。?/td> | 219K |
| 代理商： | EBD10RD4ADFA-7A |
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EBD10RD4ADFA
Data Sheet E0430E20 (Ver. 2.0)
12
Pin Capacitance (TA = +25°C, VDD = 2.5V ± 0.2V)
Parameter
Symbol
Pins
max.
Unit
Notes
Input capacitance
CI1
Address, /RAS, /CAS, /WE,
/CS, CKE
CK, /CK
12
pF
1, 3
Input capacitance
CI2
20
pF
1, 3
Data and DQS input/output
capacitance
Notes: 1. These parameters are measured on conditions: f = 100MHz, VOUT = VDDQ/2,
VOUT = 0.2V.
2. Dout circuits are disabled.
3. This parameter is sampled and not 100% tested.
CO
DQ, DQS, CB
15
pF
1, 2, 3
AC Characteristics (TA = 0 to +70
°
C, VDD, VDDQ = 2.5V ± 0.2V, VSS = 0V)
(DDR SDRAM Component Specification)
-6B
-7A
-7B
Parameter
Symbol min.
max
min.
max
min.
max
Unit Notes
Clock cycle time
(CL = 2)
(CL = 2.5)
tCK
7.5
12
7.5
12
10
12
ns
10
tCK
6
12
7.5
12
7.5
12
ns
CK high-level width
tCH
0.45
0.55
0.45
0.55
0.45
0.55
tCK
CK low-level width
tCL
0.45
0.55
0.45
0.55
0.45
0.55
tCK
CK half period
tHP
min
(tCH, tCL)
—
min
(tCH, tCL)
—
min
(tCH, tCL)
—
tCK
DQ output access time from
CK, /CK
DQS output access time from CK,
/CK
DQS to DQ skew
tAC
–0.7
0.7
–0.75
0.75
–0.75
0.75
ns
2, 11
tDQSCK –0.6
0.6
–0.75
0.75
–0.75
0.75
ns
2, 11
tDQSQ
—
0.45
—
0.5
—
0.5
ns
3
DQ/DQS output hold time from
DQS
tQH
tHP – tQHS —
tHP – tQHS —
tHP – tQHS —
ns
Data hold skew factor
tQHS
—
0.55
—
0.75
—
0.75
ns
Data-out high-impedance time
from CK, /CK
Data-out low-impedance time from
CK, /CK
tHZ
–0.7
0.7
–0.75
0.75
–0.75
0.75
ns
5, 11
tLZ
–0.7
0.7
–0.75
0.75
–0.75
0.75
ns
6, 11
Read preamble
tRPRE
0.9
1.1
0.9
1.1
0.9
1.1
tCK
Read postamble
tRPST
0.4
0.6
0.4
0.6
0.4
0.6
tCK
DQ and DM input setup time
tDS
0.45
—
0.5
—
0.5
—
ns
8
DQ and DM input hold time
tDH
0.45
—
0.5
—
0.5
—
ns
8
DQ and DM input pulse width
tDIPW
1.75
—
1.75
—
1.75
—
ns
7
Write preamble setup time
tWPRES 0
—
0
—
0
—
ns
Write preamble
tWPRE 0.25
—
0.25
—
0.25
—
tCK
Write postamble
tWPST
0.4
0.6
0.4
0.6
0.4
0.6
tCK 9
Write command to first DQS
latching transition
tDQSS
0.75
1.25
0.75
1.25
0.75
1.25
tCK
DQS falling edge to CK setup time tDSS
0.2
—
0.2
—
0.2
—
tCK
DQS falling edge hold time from
CK
tDSH
0.2
—
0.2
—
0.2
—
tCK
DQS input high pulse width
tDQSH
0.35
—
0.35
—
0.35
—
tCK
DQS input low pulse width
tDQSL
0.35
—
0.35
—
0.35
—
tCK
Address and control input setup
time
tIS
0.75
—
0.9
—
0.9
—
ns
8
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| EBD10RD4ADFA-7A-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:1GB Registered DDR SDRAM DIMM (128M words x72 bits, 1 Rank) |
| EBD10RD4ADFA-7B | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:1GB Registered DDR SDRAM DIMM (128M words x72 bits, 1 Rank) |
| EBD10RD4ADFA-7B-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:1GB Registered DDR SDRAM DIMM (128M words x72 bits, 1 Rank) |
| EBD10RD4ADFA-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:1GB Registered DDR SDRAM DIMM (128M words x72 bits, 1 Rank) |
| EBD11ED8ABFA | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:1GB Unbuffered DDR SDRAM DIMM |
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