參數(shù)資料
型號(hào): EB402
英文描述: EB402 Evaluation Board user's guide 7/01
中文描述: EB402評(píng)估板用戶指南7月1日
文件頁(yè)數(shù): 54/84頁(yè)
文件大?。?/td> 1014K
代理商: EB402
3.75 pc
10.25 pc
11.25 pc
38.25 pc
4.333 pc
48.583 pc
52.5 pc
34.5 pc
44.25 pc
5-4
Board Layout and Jumper Settings
JP12
BYP
PLLBYPASS – Remove this
jumper to bypass the on-chip
PLL, and use CLKIN for the
processor clock.
Gnd
PLLBYPA
SS pull-up
N/A
Installed
JP13
IC1-A
This jumper lets ICS1N
enable the asynchronous
SRAM.
ICSN1
SRAMEN/
N/A
Pins 1–2
JP14
D0-SB
This jumper lets DCS0N
enable the SyncBurst SRAM.
SBSRAMEN/
DCS0N
N/A
Pins 1–2
JP15
A18
Flash address 18 – Install
jumper to access upper 256
Kwords of address space.
Flash
address
18 pull-up
Gnd
N/A
Open
JP16
D1-A
This jumper lets DCS1N
enable asynchronous SRAM.
SRAMEN/
DCS1N
N/A
Pins 1–2
JP17
D2-F
This jumper lets DCS2N
enable ash memory.
FLASHEN/
DCS2N
N/A
Open
JP18
XBOOT
Selects ash memory or
asynchronous SRAM as the
XBUS boot device.
FLASHEN/
ICSN0
SRAMEN/
Pins 1–2
JP19
D3-XEN
This jumper lets DCS3N
enable the EEI. To enable the
EEI with another chip select,
or combination thereof,
connect the chip enables
together at this point.
XEN/
DCS3N
N/A
Pins 1–2
JP20
FPV
This jumper enables ash
memory erase and write
operations.
Flash VPP
+3.3 V
N/A
Pins 1–2
JP21
A16
Selects pull-up or pull-down
termination for ADDR16.
Pull-up
ADDR16
Pull-down
Pins 1–2
JP22
A17
Selects pull-up or pull-down
termination for ADDR17.
Pull-up
ADDR17
Pull-down
Pins 1–2
Table 5.1
Evaluation Board Jumper Settings and Descriptions (Cont.)
No.
Label
Description
Pin 1
Pin 2
Pin 3
Default
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