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參數(shù)資料
| 型號(hào)： | EB402 |
| 英文描述： | EB402 Evaluation Board user＇s guide 7/01 |
| 中文描述： | EB402評(píng)估板用戶指南7月1日 |
| 文件頁數(shù)： | 20/84頁 |
| 文件大?。?/td> | 1014K |
| 代理商： | EB402 |
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Clock and Control Signals
3-5
Important:
PLLSEL[3:0] = 0b1111 is reserved for test, so do not set
the PLLSEL switch to position F.
3.1.5 RSTN (Device Reset)
RSTN is the Device Reset input to the LSI402ZX. RSTN is driven by the
EB402 SYSRESETN signal. The output voltages of the EB402 power
supplies are monitored by circuits that generate a system reset signal if
a power supply voltage drops below its low-voltage threshold. The
open-drain outputs of both power monitors are connected, in a wired-OR
conguration, to a single 1 k
pull-up resistor. Figure 3.1 shows
these connections.
A MAX6337 power monitor is connected to the 1.8 V supply and
generates a reset signal if the output voltage drops below 1.6 V. The
power monitor holds SYSRESETN LOW for 100 ms. The reset input of
the power monitor is pulled-up internally and has no external connection.
A MAX6315 power monitor is connected to the 3.3 V supply to generate
a reset signal if the output voltage drops below 2.6 V. A normally-open
momentary push-button switch, S1, is connected to the Master Reset
(MRN) input of the power monitor. When activated, the switch causes the
power monitor to trigger a reset signal to the LSI402ZX. The power
monitor holds SYSRESETN LOW for 1.12 seconds.
SYSRESETN is inverted and routed to the EB402 on-board UART to
reset serial communications. For test purposes, SYSRESETN is
connected to J8, which is the control connector for the EEI.
A
0b1010
20.0
B
0b1011
21.0
C
0b1100
22.0
D
0b1101
23.0
E
0b1110
24.0
F
0b1111
Reserved
Table 3.1
PLL Multiplier Selections (Cont.)
S2 Position
PLLSEL[3:0]
CLKIN Multiplier
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