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參數(shù)資料
| 型號(hào)： | MPC604E |
| 廠商： | Motorola, Inc. |
| 英文描述： | PowerPC 604e-TM RISC Microprocessor Technical Summary |
| 中文描述： | 的PowerPC 604e -商標(biāo)RISC微處理器技術(shù)總結(jié) |
| 文件頁數(shù)： | 16/34頁 |
| 文件大?。?/td> | 117K |
| 代理商： | MPC604E |
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PowerPC 604e RISC Microprocessor Technical Summary
as three address tenures to be outstanding before a data tenure is initiated. Address tenures for address-only
transactions can exceed this limit.
Typically, memory accesses are weakly-ordered. Sequences of operations, including load/store string/
multiple instructions, do not necessarily complete in the same order in which they began—maximizing the
efficiency of the bus without sacrificing coherency of the data. The 604e allows load operations to precede
store operations (except when a dependency exists, of course). In addition, the 604e provides a separate
queue for snoop push operations so these operations can access the bus ahead of previously queued
operations. The 604e dynamically optimizes run-time ordering of load/store traffic to improve overall
performance.
In addition, the 604e implements a data bus write-only signal (DBWO) that can be used for reordering write
operations. Asserting DBWO causes the first write operation to occur before any read operations on a given
processor. Although this may be used with any write operations, it can also be used to reorder a snoop push
operation.
Access to the system interface is granted through an external arbitration mechanism that allows devices to
compete for bus mastership. This arbitration mechanism is flexible, allowing the 604e to be integrated into
systems that use various fairness and bus-parking procedures to avoid arbitration overhead. Additional
multiprocessor support is provided through coherency mechanisms that provide snooping, external control
of the on-chip caches and TLBs, and support for a secondary cache. The PowerPC architecture provides the
load/store with reservation instruction pair (
lwarx
operations useful in multiprocessor implementations.
/
stwcx.
) for atomic memory references and other
The following sections describe the 604e bus support for memory and direct-store operations. Note that
some signals perform different functions depending upon the addressing protocol used.
1.2.11.1 Memory Accesses
Memory accesses allow transfer sizes of 8, 16, 24, 32, 40, 48, 56, or 64 bits in one bus clock cycle. Data
transfers occur in either single-beat transactions or four-beat burst transactions. A single-beat transaction
transfers as much as 64 bits. Single-beat transactions are caused by noncached accesses that access memory
directly (that is, reads and writes when caching is disabled, caching-inhibited accesses, and stores in write-
through mode). Burst transactions, which always transfer an entire cache block (32 bytes), are initiated
when a block in the cache is read from or written to memory. Additionally, the 604e supports address-only
transactions used to invalidate entries in other processors’ TLBs and caches.
Typically I/O accesses are performed using the same protocol as memory accesses.
1.2.11.2 Signals
The 604e’s signals are grouped as follows:
Address arbitration signals—The 604e uses these signals to arbitrate for address bus mastership.
Address start signals—These signals indicate that a bus master has begun a transaction on the
address bus.
Address transfer signals—These signals, which consist of the address bus, address parity, and
address parity error signals, are used to transfer the address and to ensure the integrity of the
transfer.
Transfer attribute signals—These signals provide information about the type of transfer, such as the
transfer size and whether the transaction is bursted, write-through, or caching-inhibited.
Address termination signals—These signals are used to acknowledge the end of the address phase
of the transaction. They also indicate whether a condition exists that requires the address phase to
be repeated.
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