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| 型號： | DS3106LN+ |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 89/92頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC TIMING LINE CARD 64-LQFP |
| 產(chǎn)品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 160 |
| 類型： | 定時卡 IC，多路復(fù)用器 |
| PLL： | 是 |
| 主要目的： | 以太網(wǎng)，SONET/SDH，Stratum，電信 |
| 輸入： | CMOS，TTL |
| 輸出： | CMOS，LVDS，LVPECL，TTL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:2 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 312.5MHz |
| 電源電壓： | 1.62 V ~ 1.98 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-LQFP |
| 供應(yīng)商設(shè)備封裝： | 64-LQFP（10x10） |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 1429 (CN2011-ZH PDF) |
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DS3106
9
5. Detailed Features
5.1
Input Clock Features
Two programmable-frequency CMOS/TTL input clocks
Input clocks accept any multiple of 2kHz up to 125MHz
All input clocks are constantly monitored by programmable activity monitors
5.2
DPLL Features
High-resolution DPLL plus three low-jitter output APLLs
Sophisticated state machine automatically transitions between free-run, locked, and holdover states
Programmable bandwidth from 18Hz to 400Hz
Separately configurable acquisition bandwidth and locked bandwidth
Programmable damping factor to balance lock time with peaking: 1.2, 2.5, 5, 10, or 20
Multiple phase detectors: phase/frequency, early/late, and multicycle
Phase/frequency locking (
±360° capture) or nearest edge phase locking (±180° capture)
Multicycle phase detection and locking (up to
±8191UI) improves jitter tolerance and lock time
High-resolution frequency and phase measurement
Holdover frequency averaging over 1 second interval
Fast detection of input clock failure and transition to holdover mode
Low-jitter frame sync (8kHz) and multiframe sync (2kHz) aligned with output clocks
5.3
Output APLL Features
Three separate clock-multiplying, jitter attenuating APLLs can simultaneously produce SONET/SDH rates,
Fast/Gigabit Ethernet rates, and 10G Ethernet rates, all locked to a common reference clock
The T0 APLL has frequency options suitable for N x 19.44MHz, N x DS1, N x E1, N x 25MHz, and
N x 62.5MHz
The T4 APLL has frequency options suitable for N x 19.44MHz, N x DS1, N x E1, N x DS2, DS3, E3,
N x 10MHz, N x 10.24MHz, N x 13MHz, N x 25MHz, and N x 62.5MHz
The T0 APLL2 produces 312.5MHz for 10G Synchronous Ethernet applications
5.4
Output Clock Features
Two output clocks: one CMOS/TTL (≤ 125MHz) and one LVDS/LVPECL (≤ 312.50MHz)
Output clock rates include 2kHz, 8kHz, N x DS1, N x E1, DS2, DS3, E3, 6.48MHz, 19.44MHz, 38.88MHz,
51.84MHz, 77.76MHz, 155.52MHz, 311.04MHz, 2.5MHz, 25MHz, 125MHz, 156.25MHz, 312.50MHz,
10MHz, 10.24MHz, 13MHz, 30.72MHz, and various multiples and submultiples of these rates
Custom clock rates also available: any multiple of 2kHz up to 77.76MHz, any multiple of 8kHz up to 311.04MHz,
and any multiple of 10kHz up to 388.79MHz
All outputs have < 1ns peak-to-peak output jitter; outputs from APLLs have < 0.5ns peak-to-peak
8kHz frame-sync and 2kHz multiframe-sync outputs have programmable polarity and pulse width, and can
be disciplined by a 2kHz or 8kHz sync input
5.5
General Features
Operates from a single external 12.800MHz local oscillator (XO or TCXO)
SPI serial microprocessor interface
Four general-purpose I/O pins
Register set can be write protected
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS3106LN+ | 功能描述:計時器和支持產(chǎn)品 Line Card Timing IC RoHS:否 制造商:Micrel 類型:Standard 封裝 / 箱體:SOT-23 內(nèi)部定時器數(shù)量:1 電源電壓-最大:18 V 電源電壓-最小:2.7 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Reel |
| DS3107FP000 | 制造商:Thomas & Betts 功能描述:30A,CON,2P3W,MG,107,125V |
| DS3107FRAB0 | 制造商:Thomas & Betts 功能描述:30A,REC,2P3W,MG,107,AB0,125,SC |
| DS3107MP000 | 制造商:Thomas & Betts 功能描述:30A,PLG,2P3W,MG,107,125V |
| DS3107MP00K | 制造商:Thomas & Betts 功能描述:30A,PLG,2P3W,MG,107,125V,CC |
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