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DS3106
82
10.2 Input Clock Timing
Table 10-6. Input Clock Timing
(VDD = 1.8V ±10%; VDDIO = 3.3V ±5%, TA = -40°C to +85°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Input Clock Duty Cycle
30
70
%
10.3 Output Clock Timing
Table 10-7. Input Clock to Output Clock Delay
INPUT
FREQUENCY
OUTPUT
FREQUENCY
INPUT CLOCK EDGE TO
OUTPUT CLOCK EDGE
DELAY (ns)
8kHz
0
± 1.5
6.48MHz
0
± 1.5
19.44MHz
0
± 1.5
25.92MHz
0
± 1.5
38.88MHz
0
± 1.5
51.84MHz
0
± 1.5
77.76MHz
0
± 1.5
155.52MHz
0
± 1.5
Table 10-8. Output Clock Phase Alignment, Frame-Sync Alignment Mode
OUTPUT
FREQUENCY
MFSYNC FALLING EDGE TO OUTPUT
CLOCK FALLING EDGE DELAY (ns)
8kHz (FSYNC)
0
± 0.5
2kHz
0
± 0.5
8kHz
0
± 0.5
1.544MHz
0
± 1.25
2.048MHz
0
± 1.25
44.736MHz
-2.0
± 1.25
34.368MHz
-2.0
± 1.25
6.48MHz
-2.0
± 1.25
19.44MHz
-2.0
± 1.25
25.92MHz
-2.0
± 1.25
38.88MHz
-2.0
± 1.25
51.84MHz
-2.0
± 1.25
77.76MHz
-2.0
± 1.25
155.52MHz
-2.0
± 1.25
311.04MHz
-2.0
± 1.25